15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications
Abstract
Compute-in-memory (CIM) parallelizes multiply-and-average (MAV) computations and reduces off-chip weight access to reduce energy consumption and latency, specifically for Al edge devices. Prior CIM approaches demonstrated tradeoffs for area, noise margin, process variation and weight precision. 6T SRAM [1]–[3] provides the smallest cell area for CIM, but cell stability limits the number of activated cells, resulting in low parallelization. 10T and twin-8T [4]–[5] isolate the read/write paths for noise margin improvement, however both require special design of the bit cell using logic layout rules, resulting in over a 2x area overhead compared to foundry yield-optimized 6T SRAMs. Furthermore, single-bit precision of weights, in prior work [1]–[4], cannot meet the requirement for high-precision operations and scalability for large neural networks.
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Most compute-in-memory or near-memory approaches based on SRAMs and digital compute do not address the energy and time costs of reloading weights, making direct side-by-side comparisons against NVM-based weight-stationary approaches difficult; several NVM compute-in-memory studies have focused on the macro-level without accounting for data transport, control or chip infrastructure costs, and are,
“Although several compute-in-memory or near-memory approaches based on SRAMs and digital compute35–38 have been presented in the literature, most of these do not address the energy and time costs of reloading weights, thus making direct side-by-side comparisons against NVM-based weight-stationary approaches difficult.”
From An analog-AI chip for energy-efficient speech recognition and transcription (2023) · cites this paper as [36]
Cites
Biswas, A., & Chandrakasan, A. P. (2018) · 2018 IEEE International Solid - State Circuits Conference - (ISSCC) · doi:10.1109/isscc.2018.8310397 · Cited by 337 · see citing works
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An analog-AI chip for energy-efficient speech recognition and transcription
Ambrogio, S., Narayanan, P., Okazaki, A., Fasoli, A., Mackin, C., Hosokawa, K., Nomura, A., Yasuda, T., Chen, A., Friz, A., et al. (2023) · Nature · doi:10.1038/s41586-023-06337-5 · Cited by 242 · see citing works
15.1 A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing
Jia, H., Ozatay, M., Tang, Y., Valavi, H., Pathak, R., Lee, J., & Verma, N. (2021) · 2021 IEEE International Solid- State Circuits Conference (ISSCC) · doi:10.1109/isscc42613.2021.9365788 · Cited by 168 · see citing works
Mixed-Signal Computing for Deep Neural Network Inference
Murmann, B. (2021) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2020.3020286 · Cited by 160 · see citing works
Li, W., Sun, X., Huang, S., Jiang, H., & Yu, S. (2022) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2022.3163197 · Cited by 77 · see citing works
On the Accuracy of Analog Neural Network Inference Accelerators
Xiao, T. P., Feinberg, B., Bennett, C. H., Prabhakar, V., Saxena, P., Agrawal, V., Agarwal, S., & Marinella, M. J. (2022) · IEEE Circuits and Systems Magazine · doi:10.1109/mcas.2022.3214409 · Cited by 76 · see citing works
- Authors
- Dong, Q., Sinangil, M. E., Erbagci, B., Sun, D., Khwa, W.-S., Liao, H.-J., Wang, Y., & Chang, J.
- Affiliations
- Taiwan Semiconductor Manufacturing Company (United States) (US)
- Taiwan Semiconductor Manufacturing Company (Taiwan) (TW)
- Venue
- 2020 IEEE International Solid- State Circuits Conference - (ISSCC)
- Publisher
- IEEE
- Published
- 2020-02
- Pages
- 242-244
- ISSN
- 0193-6530 (ISSN-L)
- OpenAlex
- W3015432327
- Cited by
- 346
- References
- 1
- Citations by year
- 2026: 24 · 2025: 51 · 2024: 61 · 2023: 63 · 2022: 61 · 2021: 68 · 2020: 17 · 2012: 1
- FWCI
- 73.47
- Type
- conference paper
- Language
- en
- Open access
- closed
- Licence
- Locations
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Keywords
- in-memory computing, SRAM macro, 6T SRAM, machine learning accelerators, 7nm FinFET, noise margin, process variation, weight precision, edge devices, energy efficiency, 10T SRAM
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