15.1 A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing

Jia, Hongyang; Ozatay, Murat; Tang, Yinqi; Valavi, Hossein; Pathak, Rakshit; Lee, Jinseok; Verma, Naveen

doi:10.1109/isscc42613.2021.9365788

Cited by 168Advanced Memory and Neural ComputingParallel Computing and Optimization TechniquesLow-power high-performance VLSI design

15.1 A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing

Jia, Hongyang, Ozatay, Murat, Tang, Yinqi, Valavi, Hossein, Pathak, Rakshit, Lee, Jinseok, Verma, Naveen·2021·2021 IEEE International Solid- State Circuits Conference (ISSCC)

DOI 10.1109/isscc42613.2021.9365788

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Abstract

This paper presents a scalable neural-network (NN) inference accelerator in 16nm, based on an array of programmable cores employing mixed-signal In-Memory Computing (IMC), digital Near-Memory Computing (NMC), and localized buffering/control. IMC achieves high energy efficiency and throughput for matrix-vector multiplications (MVMs), which dominate NNs; but, scalability poses numerous challenges, both technologically, going to advanced nodes to maintain gains over digital architectures, and architecturally, for full execution of diverse NNs. Recent demonstrations have explored integrating IMC in programmable processors [1, 2], but have not achieved IMC efficiency and throughput for full executions. The central challenge is drastically different physical design points and associated tradeoffs incurred by IMC compared to digital engines. Namely, IMC substantially increases compute energy efficiency and HW density/parallelism, but retains the overheads of HW virtualization (state and data swapping/buffering/communication across spatial/temporal computation mappings). The demonstrated architecture is co-designed with SW-mapping algorithms (encapsulated in a custom graph compiler), to provide efficiency across a broad range of mapping strategies, to overcome these overheads.

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Most compute-in-memory or near-memory approaches based on SRAMs and digital compute do not address the energy and time costs of reloading weights, making direct side-by-side comparisons against NVM-based weight-stationary approaches difficult; several NVM compute-in-memory studies have focused on the macro-level without accounting for data transport, control or chip infrastructure costs, and are,
“Although several compute-in-memory or near-memory approaches based on SRAMs and digital compute35–38 have been presented in the literature, most of these do not address the energy and time costs of reloading weights, thus making direct side-by-side comparisons against NVM-based weight-stationary approaches difficult.”
From An analog-AI chip for energy-efficient speech recognition and transcription (2023) · cites this paper as [35]

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Scalable and Programmable Neural Network Inference Accelerator Based on In-Memory Computing
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Self-citation

Authors: Jia, H., Ozatay, M., Tang, Y., Valavi, H., Pathak, R., Lee, J., & Verma, N.
Affiliations: Princeton University (US)
ORCID: Jia, Hongyang
Ozatay, Murat
Tang, Yinqi
Valavi, Hossein
Lee, Jinseok
Verma, Naveen
Venue: 2021 IEEE International Solid- State Circuits Conference (ISSCC)
Publisher: IEEE
Published: 2021-02-13
Pages: 236-238
ISSN: 0193-6530 (ISSN-L)
DOI: 10.1109/isscc42613.2021.9365788
OpenAlex: W3135835558
Cited by: 168
References: 10
Citations by year: 2026: 11 · 2025: 28 · 2024: 30 · 2023: 45 · 2022: 43 · 2021: 11
FWCI: 50.63
Type: conference paper
Language: en
Open access: closed
Licence: ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html (vor)
doi.org/10.15223/policy-029 (stm-asf)
doi.org/10.15223/policy-037 (stm-asf)
Locations: Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference (publishedVersion)
Topics: Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
Keywords: in-memory computing, near-memory computing, matrix-vector multiplication, energy efficiency, scalable hardware architecture

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15.1 A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing

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