The DOI matches its Crossref record; 10 of the 10 references it cites were found in a registry or an index.
15.1 A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing
Abstract
This paper presents a scalable neural-network (NN) inference accelerator in 16nm, based on an array of programmable cores employing mixed-signal In-Memory Computing (IMC), digital Near-Memory Computing (NMC), and localized buffering/control. IMC achieves high energy efficiency and throughput for matrix-vector multiplications (MVMs), which dominate NNs; but, scalability poses numerous challenges, both technologically, going to advanced nodes to maintain gains over digital architectures, and architecturally, for full execution of diverse NNs. Recent demonstrations have explored integrating IMC in programmable processors [1, 2], but have not achieved IMC efficiency and throughput for full executions. The central challenge is drastically different physical design points and associated tradeoffs incurred by IMC compared to digital engines. Namely, IMC substantially increases compute energy efficiency and HW density/parallelism, but retains the overheads of HW virtualization (state and data swapping/buffering/communication across spatial/temporal computation mappings). The demonstrated architecture is co-designed with SW-mapping algorithms (encapsulated in a custom graph compiler), to provide efficiency across a broad range of mapping strategies, to overcome these overheads.
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“Although several compute-in-memory or near-memory approaches based on SRAMs and digital compute35–38 have been presented in the literature, most of these do not address the energy and time costs of reloading weights, thus making direct side-by-side comparisons against NVM-based weight-stationary approaches difficult.”
From An analog-AI chip for energy-efficient speech recognition and transcription (2023) · cites this paper as [35]
Citations
Cites
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
Chen, Y.-H., Krishna, T., Emer, J. S., & Sze, V. (2017) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2016.2616357 · Cited by 3,247
14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks
Chen, Y., Krishna, T., Emer, J., & Sze, V. (2016) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.2016.7418007 · Cited by 713
Dong, Q., Sinangil, M. E., Erbagci, B., Sun, D., Khwa, W.-S., Liao, H.-J., Wang, Y., & Chang, J. (2020) · 2020 IEEE International Solid- State Circuits Conference - (ISSCC) · doi:10.1109/isscc19947.2020.9062985 · Cited by 346
A 64-Tile 2.4-Mb In-Memory-Computing CNN Accelerator Employing Charge-Domain Compute
Valavi, H., Ramadge, P. J., Nestler, E., & Verma, N. (2019) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2019.2899730 · Cited by 328
Self-citationA Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing
Jia, H., Valavi, H., Tang, Y., Zhang, J., & Verma, N. (2020) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2020.2987714 · Cited by 233
Self-citationBankman, D. J., Yang, L., Moons, B., Verhelst, M., & Murmann, B. (2018) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.2018.8310264 · Cited by 158
Wang, J., Wang, X., Eckert, C. A., Subramaniyan, A. K., Das, R., Blaauw, D. T., & Sylvester, D. (2019) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.2019.8662419 · Cited by 141
Yue, J., Yuan, Z., Feng, X., He, Y., Zhang, Z., Si, X., Liu, R., Chang, M., Li, X., Yang, H., et al. (2020) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc19947.2020.9062958 · Cited by 141
Guo, R., Liu, Y., Zheng, S., Wu, S.-Y., Ouyang, P., Khwa, W.-S., Chen, X., Chen, J., Li, X., Liu, L., et al. (2019) · Symposium on VLSI Circuits · doi:10.23919/vlsic.2019.8778028 · Cited by 101
7.2 A 12nm Programmable Convolution-Efficient Neural-Processing-Unit Chip Achieving 825TOPS
Jiao, Y., Han, L., Jin, R., Yi-Jung, S., Ho, C., Li, Y., Li, Y., Chen, L., Chen, Z., Liu, L., et al. (2020) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc19947.2020.9062984 · Cited by 59
Cited by
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Memristive technologies for data storage, computation, encryption, and radio-frequency communication
Lanza, M., Sebastian, A., Lu, W. D., Gallo, M. L., Chang, M., Akinwande, D., Puglisi, F. M., Alshareef, H. N., Liu, M., & Roldán, J. B. (2022) · Science · doi:10.1126/science.abj9979 · Cited by 732
An analog-AI chip for energy-efficient speech recognition and transcription
Ambrogio, S., Narayanan, P., Okazaki, A., Fasoli, A., Mackin, C., Hosokawa, K., Nomura, A., Yasuda, T., Chen, A., Friz, A., et al. (2023) · Nature · doi:10.1038/s41586-023-06337-5 · Cited by 269
Khaddam-Aljameh, R., Stanisavljevic, M., Fornt Mas, J., Karunaratne, G., Brändli, M., Liu, F., Singh, A., Müller, S. M., Egger, U., Petropoulos, A., et al. (2022) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2022.3140414 · Cited by 144
Wang, D., Lin, C.-T., Chen, G. K., Knag, P. C., Krishnamurthy, R. K., & Seok, M. (2022) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc42614.2022.9731659 · Cited by 119
DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC
Ueyoshi, K., Papistas, I. A., Houshmand, P., Sarda, G. M., Jain, V., Shi, M., Zheng, Q., Giraldo, S., Vrancx, P., Doevenspeck, J., et al. (2022) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc42614.2022.9731716 · Cited by 89
Metadata
- Authors
- Jia, H., Ozatay, M., Tang, Y., Valavi, H., Pathak, R., Lee, J., & Verma, N.
- Affiliations
- Princeton University (US)
- Venue
- 2021 IEEE International Solid- State Circuits Conference (ISSCC)
- Publisher
- IEEE
- Published
- 2021-02-13
- Pages
- 236-238
- ISSN
- 0193-6530 (ISSN-L)
- OpenAlex
- W3135835558
- Cited by
- 168
- References
- 10
- Citations by year
- 2026: 11 · 2025: 28 · 2024: 30 · 2023: 45 · 2022: 43 · 2021: 11
- FWCI
- 50.63
- Type
- conference paper
- Language
- en
- Open access
- closed
- Licence
- Locations
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Keywords
- in-memory computing, near-memory computing, matrix-vector multiplication, energy efficiency, scalable hardware architecture
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