15.1 A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing

Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks

Chen, Y.-H., Krishna, T., Emer, J. S., & Sze, V. (2017) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2016.2616357 · Cited by 3,247

14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks

Chen, Y., Krishna, T., Emer, J., & Sze, V. (2016) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.2016.7418007 · Cited by 713

15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications

Dong, Q., Sinangil, M. E., Erbagci, B., Sun, D., Khwa, W.-S., Liao, H.-J., Wang, Y., & Chang, J. (2020) · 2020 IEEE International Solid- State Circuits Conference - (ISSCC) · doi:10.1109/isscc19947.2020.9062985 · Cited by 346

A 64-Tile 2.4-Mb In-Memory-Computing CNN Accelerator Employing Charge-Domain Compute

Valavi, H., Ramadge, P. J., Nestler, E., & Verma, N. (2019) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2019.2899730 · Cited by 328

A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing

Jia, H., Valavi, H., Tang, Y., Zhang, J., & Verma, N. (2020) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2020.2987714 · Cited by 233

An always-on 3.8μJ/86% CIFAR-10 mixed-signal binary CNN processor with all memory on chip in 28nm CMOS

Bankman, D. J., Yang, L., Moons, B., Verhelst, M., & Murmann, B. (2018) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.2018.8310264 · Cited by 158

14.2 A Compute SRAM with Bit-Serial Integer/Floating-Point Operations for Programmable In-Memory Vector Acceleration

Wang, J., Wang, X., Eckert, C. A., Subramaniyan, A. K., Das, R., Blaauw, D. T., & Sylvester, D. (2019) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.2019.8662419 · Cited by 141

14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse

Yue, J., Yuan, Z., Feng, X., He, Y., Zhang, Z., Si, X., Liu, R., Chang, M., Li, X., Yang, H., et al. (2020) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc19947.2020.9062958 · Cited by 141

A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS

Guo, R., Liu, Y., Zheng, S., Wu, S.-Y., Ouyang, P., Khwa, W.-S., Chen, X., Chen, J., Li, X., Liu, L., et al. (2019) · Symposium on VLSI Circuits · doi:10.23919/vlsic.2019.8778028 · Cited by 101

7.2 A 12nm Programmable Convolution-Efficient Neural-Processing-Unit Chip Achieving 825TOPS

Jiao, Y., Han, L., Jin, R., Yi-Jung, S., Ho, C., Li, Y., Li, Y., Chen, L., Chen, Z., Liu, L., et al. (2020) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc19947.2020.9062984 · Cited by 59

Memristive technologies for data storage, computation, encryption, and radio-frequency communication

Lanza, M., Sebastian, A., Lu, W. D., Gallo, M. L., Chang, M., Akinwande, D., Puglisi, F. M., Alshareef, H. N., Liu, M., & Roldán, J. B. (2022) · Science · doi:10.1126/science.abj9979 · Cited by 732

An analog-AI chip for energy-efficient speech recognition and transcription

Ambrogio, S., Narayanan, P., Okazaki, A., Fasoli, A., Mackin, C., Hosokawa, K., Nomura, A., Yasuda, T., Chen, A., Friz, A., et al. (2023) · Nature · doi:10.1038/s41586-023-06337-5 · Cited by 269

HERMES-Core—A 1.59-TOPS/mm 2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Khaddam-Aljameh, R., Stanisavljevic, M., Fornt Mas, J., Karunaratne, G., Brändli, M., Liu, F., Singh, A., Müller, S. M., Egger, U., Petropoulos, A., et al. (2022) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2022.3140414 · Cited by 144

DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware

Wang, D., Lin, C.-T., Chen, G. K., Knag, P. C., Krishnamurthy, R. K., & Seok, M. (2022) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc42614.2022.9731659 · Cited by 119

DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC

Ueyoshi, K., Papistas, I. A., Houshmand, P., Sarda, G. M., Jain, V., Shi, M., Zheng, Q., Giraldo, S., Vrancx, P., Doevenspeck, J., et al. (2022) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc42614.2022.9731716 · Cited by 89

Fully On-Chip MAC at 14 nm Enabled by Accurate Row-Wise Programming of PCM-Based Weights and Parallel Vector-Transport in Duration-Format

Narayanan, P., Ambrogio, S., Okazaki, A., Hosokawa, K., Tsai, H., Nomura, A., Yasuda, T., Mackin, C., Lewis, S. C., Friz, A., et al. (2021) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2021.3115993 · Cited by 85

7.8 A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing

Chen, P., Wu, M., Zhao, W., Cui, J., Wang, Z., Zhang, Y., Wang, Q., Ru, J., Shen, L., Jia, T., et al. (2023) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc42615.2023.10067289 · Cited by 84

TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks

Song, J., Wang, Y., Guo, M., Ji, X. L., Cheng, K., Hu, Y., Tang, X., Wang, R., & Huang, R. (2021) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2021.3083275 · Cited by 81

Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives

Su, F., Liu, C., & Stratigopoulos, H. (2023) · IEEE Design and Test · doi:10.1109/mdat.2023.3241116 · Cited by 84

STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse

Yue, J., Liu, Y., Yuan, Z., Feng, X., He, Y., Sun, W., Zhang, Z., Si, X., Liu, R., Wang, Z., et al. (2022) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2022.3148273 · Cited by 78

A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh

Jain, S., Tsai, H., Chen, C.-T., Muralidhar, R., Boybat, I., Frank, M. M., Woźniak, S., Stanisavljevic, M., Adusumilli, P., Narayanan, P., et al. (2023) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2022.3221390 · Cited by 76

184QPS/W 64Mb/mm 2 3D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System

Niu, D., Li, S., Wang, Y., Han, W., Zhang, Z., Guan, Y., Guan, T., Sun, F., Xue, F., Duan, L., et al. (2022) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc42614.2022.9731694 · Cited by 74

7.6 A 70.85-86.27TOPS/W PVT-Insensitive 8b Word-Wise ACIM with Post-Processing Relaxation

Hsieh, S.-E., Wei, C.-H., Xue, C.-X., Lin, H.-W., Tu, W.-H., Chang, E.-J., Yang, K.-T., Chen, P.-H., Liao, W.-N., Low, L. L., et al. (2023) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc42615.2023.10067335 · Cited by 68

7.3 A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference

He, Y., Diao, H., Tang, C., Jia, W., Tang, X., Wang, Y., Yue, J., Li, X., Yang, H., Jia, H., et al. (2023) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc42615.2023.10067305 · Cited by 68

A review on SRAM-based computing in-memory: Circuits, functions, and applications

Lin, Z., Tong, Z., Zhang, J., Wang, F., Tian, X., Zhao, Y., Wu, X., Peng, C., Lu, W., Zhao, Q., et al. (2022) · Journal of Semiconductors · doi:10.1088/1674-4926/43/3/031401 · Cited by 61

Digital Versus Analog Artificial Intelligence Accelerators: Advances, trends, and emerging designs

Seo, J.-S., Saikia, J., Meng, J., He, W., Suh, H.-S., Anupreetham, A., Liao, Y., Hasssan, A., & Yeo, I. (2022) · IEEE Solid-State Circuits Magazine · doi:10.1109/mssc.2022.3182935 · Cited by 61

16.7 A 40-310TOPS/W SRAM-Based All-Digital Up to 4b In-Memory Computing Multi-Tiled NN Accelerator in FD-SOI 18nm for Deep-Learning Edge Applications

Desoli, G., Chawla, N., Boesch, T., Avodhyawasi, M., Rawat, H., Chawla, H., Abhijith, V., Paolo, Z., Sharma, A., Cappetta, C., et al. (2023) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc42615.2023.10067422 · Cited by 56

COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning

Zhu, H., Jiao, B., Zhang, J., Jia, X., Wang, Y., Guan, T., Wang, S., Niu, D., Zheng, H., Chen, C., et al. (2022) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc42614.2022.9731657 · Cited by 53

Neuro-CIM: ADC-Less Neuromorphic Computing-in-Memory Processor With Operation Gating/Stopping and Digital–Analog Networks

Kim, S., Kim, S., Um, S., Kim, S., Kim, K., & Yoo, H. (2023) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2023.3273238 · Cited by 51

Benchmarking In-Memory Computing Architectures

Shanbhag, N. R., & Roy, S. K. (2022) · IEEE Open Journal of the Solid-State Circuits Society · doi:10.1109/ojsscs.2022.3210152 · Cited by 57

A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks

Kim, H., Mu, J., Yu, C., Kim, T. T.-H., & Kim, B. (2023) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2022.3232648 · Cited by 47

In-Memory Computing for Machine Learning and Deep Learning

Lepri, N., Glukhov, A., Cattaneo, L., Farronato, M., Mannocci, P., & Ielmini, D. (2023) · IEEE Journal of the Electron Devices Society · doi:10.1109/jeds.2023.3265875 · Cited by 52

Precision of bit slicing with in-memory computing based on analog phase-change memory crossbars

Gallo, M. L., Nandakumar, S. R., Ciric, L., Boybat, I., Khaddam-Aljameh, R., Mackin, C., & Sebastian, A. (2022) · Neuromorphic Computing and Engineering · doi:10.1088/2634-4386/ac4fb7 · Cited by 43

Hardware Design and Verification with Large Language Models: A Scoping Review, Challenges, and Open Issues

Abdollahi, M., Yeganli, S. F., Baharloo, M. M., & Baniasadi, A. (2024) · Electronics · doi:10.3390/electronics14010120 · Cited by 53

10T SRAM Computing-in-Memory Macros for Binary and Multibit MAC Operation of DNN Edge Processors

Nguyen, V. T., Kim, J.-S., & Lee, J. (2021) · IEEE Access · doi:10.1109/access.2021.3079425 · Cited by 43

IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm2 CIM-SRAM With Multi-Bit Analog Batch-Normalization

Kneip, A., Lefebvre, M., Verecken, J., & Bol, D. (2023) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2023.3269098 · Cited by 39

Trending IC design directions in 2022

Chan, C., Cheng, L., Deng, W., Feng, P., Li, G., Huang, M., Jia, H., Jie, L., Lei, K., Liu, X., et al. (2022) · Journal of Semiconductors · doi:10.1088/1674-4926/43/7/071401 · Cited by 38

Combined HW/SW Drift and Variability Mitigation for PCM-Based Analog In-Memory Computing for Neural Network Applications

Antolini, A., Paolino, C., Zavalloni, F., Lico, A., Scarselli, E. F., Mangia, M., Pareschi, F., Setti, G., Rovatti, R., Torres, M. L., et al. (2023) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2023.3241750 · Cited by 40

SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity- Compensated Fully Parallel Analog Adder Tree

Chen, Y., Yin, G., Zhou, M., Tang, W., Yang, Z., Lee, M., Du, X., Yue, J., Liu, J., Yang, H., et al. (2023) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2023.3266269 · Cited by 35

A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro

Song, J., Tang, X., Qiao, X., Wang, Y., Wang, R., & Huang, R. (2023) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2023.3244338 · Cited by 35

ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays

Jiang, H., Huang, S., Li, W., & Yu, S. (2022) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2022.3208755 · Cited by 35

Comprehending In-memory Computing Trends via Proper Benchmarking

Shanbhag, N. R., & Roy, S. K. (2022) · Custom Integrated Circuits Conference · doi:10.1109/cicc53496.2022.9772817 · Cited by 33

A Survey of Computing-in-Memory Processor: From Circuit to Application

Sun, W., Yue, J., He, Y., Huang, Z., Wang, J., Jia, W., Li, Y., Lei, L., Jia, H., & Liu, Y. (2023) · IEEE Open Journal of the Solid-State Circuits Society · doi:10.1109/ojsscs.2023.3328290 · Cited by 32

ML-HW Co-Design of Noise-Robust TinyML Models and Always-On Analog Compute-in-Memory Edge Accelerator

Zhou, C., Garćıa-Redondo, F., Büchel, J., Boybat, I., Comas, X. T. I., Nandakumar, S. R., Das, S., Sebastian, A., Gallo, M. L., & Whatmough, P. N. (2022) · IEEE Micro · doi:10.1109/mm.2022.3198321 · Cited by 44

A 818–4094 TOPS/W Capacitor-Reconfigured Analog CIM for Unified Acceleration of CNNs and Transformers

Yoshioka, K. (2024) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2024.3457898 · Cited by 29

Extreme Partial-Sum Quantization for Analog Computing-In-Memory Neural Network Accelerators

Kim, Y., Kim, H., & Kim, J. (2022) · ACM Journal on Emerging Technologies in Computing Systems · doi:10.1145/3528104 · Cited by 28

A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture

Yan, S., Yue, J., He, C., Wang, Z. X., Cong, Z., He, Y., Zhou, M., Sun, W., Li, X., Dou, C., et al. (2024) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2024.3363871 · Cited by 28

CIMFormer: A Systolic CIM-Array-Based Transformer Accelerator With Token-Pruning-Aware Attention Reformulating and Principal Possibility Gathering

Guo, R., Chen, X. L., Wang, L., Wang, Y., Sun, H., Wei, J., Han, H., Liu, L., Wei, S., Hu, Y., et al. (2024) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2024.3402174 · Cited by 33

A neuromorphic processor with on-chip learning for beyond-CMOS device integration

Greatorex, H., Richter, O., Mastella, M., Cotteret, M., Klein, P., Fabre, M., Rubino, A., Girão, W. S., Chen, J.-R., Ziegler, M., et al. (2025) · Nature Communications · doi:10.1038/s41467-025-61576-6 · Cited by 34

TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization

Guo, R., Yue, Z., Si, X., Li, H., Hu, T., Tang, L., Wang, Y., Sun, H., Liu, L., Chang, M., et al. (2022) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2022.3198413 · Cited by 28

An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update

Yue, J., Liu, Y., Feng, X., He, Y., Wang, J., Yuan, Z., Zhan, M., Liu, J., Su, J.-W., Chung, Y.-L., et al. (2023) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2023.3324954 · Cited by 28

An In-Memory-Computing Charge-Domain Ternary CNN Classifier

Yang, X., Zhu, K., Tang, X., Wang, M., Zhan, M., Lu, N., Kulkarni, J. P., Pan, D. Z., Liu, Y., & Sun, N. (2023) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2023.3238725 · Cited by 26

An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMOS

Chen, G. K., Knag, P. C., Tokunaga, C., & Krishnamurthy, R. K. (2022) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2022.3228765 · Cited by 27

A 28-nm 18.7 TOPS/mm² 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh

Zhan, Y., Yu, W.-H., Un, K.-F., Martins, R. P., & Mak, P. (2024) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2024.3387995 · Cited by 22

A Fully Row/Column-Parallel In-Memory Computing Macro in Foundry MRAM With Differential Readout for Noise Rejection

Deaville, P., Zhang, B., & Verma, N. (2024) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2024.3386462 · Cited by 21

A 4-Bit Mixed-Signal MAC Macro With One-Shot ADC Conversion

Yang, X., & Sun, N. (2023) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2023.3269076 · Cited by 22

From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits

Zhang, Z., Chen, J., Chen, X., Guo, A., Wang, B., Xiong, T., Kong, Y., Pu, X., He, S., Si, X., et al. (2023) · Science China Information Sciences · doi:10.1007/s11432-023-3800-9 · Cited by 20

A 16.38TOPS and 4.55POPS/W SRAM Computing-in-Memory Macro for Signed Operands Computation and Batch Normalization Implementation

Qiao, X., Guo, Q., Tang, X., Song, J., Wei, R., Li, M., Wang, R., & Wang, Y. (2024) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2024.3353464 · Cited by 19

A 22-nm Delta-Sigma Computing-In-Memory SRAM Macro With Near-Zero-Mean Outputs and LSB-First ADCs for Edge AI Processing

Chen, P., Zhao, W., Wu, M., Shen, L., Jia, T., Huang, R., Ye, L., & Ma, Y. (2025) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2025.3539736 · Cited by 19

ARBiS: A Hardware-Efficient SRAM CIM CNN Accelerator With Cyclic-Shift Weight Duplication and Parasitic-Capacitance Charge Sharing for AI Edge Application

Zhao, C., Fang, J., Jiang, J., Xue, X., & Zeng, X. (2022) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2022.3215535 · Cited by 19

BR-CIM: An Efficient Binary Representation Computation-In-Memory Design

Yue, Z., Wang, Y., Qin, Y., Liu, L., Wei, S., & Yin, S. (2022) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2022.3185135 · Cited by 18

ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning

Klein, J. A. H., Boybat, I., Qureshi, Y. M., Dazzi, M., Levisse, A., Ansaloni, G., Zapater, M., Sebastian, A., & Atienza, D. (2022) · IEEE Transactions on Computers · doi:10.1109/tc.2022.3230285 · Cited by 18

An In-Memory Computing SRAM Macro for Memory-Augmented Neural Network

Kim, S., Lee, W., Kim, S., Park, S., & Jeon, D. (2021) · IEEE Transactions on Circuits & Systems II Express Briefs · doi:10.1109/tcsii.2021.3132063 · Cited by 18

SPCIM: Sparsity-Balanced Practical CIM Accelerator With Optimized Spatial-Temporal Multi-Macro Utilization

Wang, Y., Tu, F., Liu, L., Wei, S., Xie, Y., & Yin, S. (2022) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2022.3216735 · Cited by 17

Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros

Sun, X., Cao, W., Crafton, B., Akarvardar, K., Mori, H., Fujiwara, H., Noguchi, H., Chih, Y.-D., Chang, M., Wang, Y., et al. (2023) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2023.3333290 · Cited by 18

DCT-RAM: A Driver-Free Process-In-Memory 8T SRAM Macro with Multi-Bit Charge-Domain Computation and Time-Domain Quantization

Chen, Z., Jin, Q., Yu, Z., Wang, Y., & Yang, K. (2022) · Custom Integrated Circuits Conference · doi:10.1109/cicc53496.2022.9772826 · Cited by 16

ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits

Zhang, W., Ando, S., Chen, Y.-C., & Yoshioka, K. (2025) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2025.3605286 · Cited by 15

ML Processors Are Going Multi-Core: A performance dream or a scheduling nightmare?

Verhelst, M., Shi, M., & Mei, L. (2022) · IEEE Solid-State Circuits Magazine · doi:10.1109/mssc.2022.3201783 · Cited by 14

Scaling-CIM: An eDRAM-based In-Memory-Computing Accelerator with Dynamic-Scaling ADC for SQNR-Boosting and Layer-wise Adaptive Bit-Truncation

Kim, S., Um, S., Jo, W., Lee, J., Ha, S., Li, Z., & Yoo, H. (2023) · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · doi:10.23919/vlsitechnologyandcir57934.2023.10185439 · Cited by 14

CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators

Qu, S., Zhao, S., Li, B., He, Y., Cai, X., Zhang, L., & Wang, Y. (2024) · International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) · doi:10.1145/3620665.3640359 · Cited by 13

Enhancing the Energy Efficiency and Robustness of tinyML Computer Vision Using Coarsely-quantized Log-gradient Input Images

Lu, Q., & Murmann, B. (2023) · ACM Transactions on Embedded Computing Systems · doi:10.1145/3591466 · Cited by 21

A Reconfigurable 1T1C eDRAM-based Spiking Neural Network Computing-In-Memory Processor for High System-Level Efficiency

Kim, S., Kim, S., Um, S., Kim, S., Li, Z., Kim, S., Jo, W., & Yoo, H. (2023) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas46773.2023.10181420 · Cited by 12

A 28-nm 135.19 TOPS/W Bootstrapped-SRAM Compute-in-Memory Accelerator With Layer-Wise Precision and Sparsity

Mao, W., Liu, D., Zhou, H., Li, F., Li, K., Wu, Q., Yang, J., Cheng, Q., Zhang, L., & Yu, H. (2024) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2024.3486322 · Cited by 12

MC2-RAM: An In-8T-SRAM Computing Macro Featuring Multi-Bit Charge-Domain Computing and ADC-Reduction Weight Encoding

Chen, Z., Jin, Q., Wang, J., Wang, Y., & Yang, K. (2021) · International Symposium on Low Power Electronics and Design (ISLPED) · doi:10.1109/islped52811.2021.9502505 · Cited by 12

Benchmarking DNN Mapping Methods for the in-Memory Computing Accelerators

Wang, Y., & Fong, X. (2023) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2023.3328864 · Cited by 11

BFP-CIM: Runtime Energy-Accuracy Scalable Computing-in-Memory-Based DNN Accelerator Using Dynamic Block-Floating-Point Arithmetic

Chang, C.-Y., Huang, C.-T., Chuang, Y.-C., Chou, K.-C., & Wu, A.-Y. A. (2023) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2023.3338378 · Cited by 12

A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations

Xiao, K., Qiao, X., Cui, X., Song, J., Luo, H., Wang, X., & Wang, Y. (2024) · IEEE Transactions on Circuits & Systems II Express Briefs · doi:10.1109/tcsii.2024.3360284 · Cited by 11

A 28-nm 28.8-TOPS/W Attention-Based NN Processor With Correlative CIM Ring Architecture and Dataflow-Reshaped Digital-Assisted CIM Array

Guo, R., Yue, Z., Wang, Y., Li, H., Hu, T., Wang, Y., Sun, H., Hsu, J.-L., Zhang, Y., Yan, B., et al. (2024) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2024.3419808 · Cited by 14

A Fully Row/Column-Parallel MRAM in-Memory Computing Macro With Memory-Resistance Boosting and Weighted Multi-Column ADC Readout

Deaville, P., Zhang, B., & Verma, N. (2024) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2024.3512360 · Cited by 11

Hybrid SRAM/ROM Compute-in-Memory Architecture for High Task-Level Energy Efficiency in Transformer Models With 8928-kb/mm² Density in 28nm CMOS

Yin, G., Chen, Y., Lee, M., Du, X., Ke, Y., Tang, W., Chen, Z., Zhou, M., Yue, J., Yang, H., et al. (2025) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2025.3556008 · Cited by 12

An INT8 Charge-Digital Hybrid Compute-In-Memory Macro With CNN-Friendly Shift-Feed Register Design

Chen, J., Zhao, Y., Xiong, T., & Si, X. (2023) · IEEE Transactions on Circuits & Systems II Express Briefs · doi:10.1109/tcsii.2023.3323211 · Cited by 11

3-D In-Sensor Computing for Real-Time DVS Data Compression: 65-nm Hardware-Algorithm Co-Design

Nair, G. R., Nalla, P. S., Krishnan, G., V, Anupreetham, A., Oh, J., Hassan, A., Yeo, I., Kasichainula, K., Seok, M., Seo, J.-S., et al. (2024) · IEEE Solid-State Circuits Letters · doi:10.1109/lssc.2024.3375110 · Cited by 10

A REVIEW OF MOBILE NETWORKS: EVOLUTION FROM 5G TO 6G

Левин, С. М. (2024) · Computer Engineering and Intelligent Systems · doi:10.7176/ceis/15-1-06 · Cited by 10

SRAM- and eDRAM-Based Compute-in-Memory Designs, Accelerators, and Evaluation Frameworks: Macro-Level and System-Level Optimization and Evaluation

He, Y., Hu, X., Jia, H., & Seo, J.-S. (2025) · IEEE Solid-State Circuits Magazine · doi:10.1109/mssc.2025.3549358 · Cited by 11

A 4-bit Mixed-Signal MAC Array with Swing Enhancement and Local Kernel Memory

Yu, W.-H., Giordano, M., Doshi, R., Zhang, M., Mak, P., Martins, R. P., & Murmann, B. (2021) · IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) · doi:10.1109/mwscas47672.2021.9531769 · Cited by 10

A Nonvolatile Compute-in-Memory Macro Using Voltage-Controlled MRAM and In Situ Magnetic-to-Digital Converter

Jacob, V. K., Yang, J., He, H., Gupta, P., Wang, K. L., & Pamarti, S. (2023) · IEEE Journal on Exploratory Solid-State Computational Devices and Circuits · doi:10.1109/jxcdc.2023.3258431 · Cited by 11

AnalogNets: ML-HW Co-Design of Noise-robust TinyML Models and Always-On Analog Compute-in-Memory AcceleratorPreprint

Zhou, C., Garćıa-Redondo, F., Büchel, J., Boybat, I., Comas, X. T. I., Nandakumar, S. R., Das, S., Sebastian, A., Gallo, M. L., & Whatmough, P. N. (2021) · arXiv (Cornell University) · doi:10.48550/arxiv.2111.06503 · Cited by 10

Dyn-Bitpool: A 28 nm 27 TOPS/W Two-Sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization

Xiang, X., Yue, Z., Zhang, X., Wei, S., Hu, Y., & Yin, S. (2025) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2025.3547001 · Cited by 9

A 22nm 29.3TOPS/W End-to-End CIM-Utilization-Aware Accelerator with Reconfigurable 4D-CIM Mapping and Adaptive Feature Reuse for Diverse CNNs and Transformers

Wang, J., Lou, M., Yanq, Z., Peng, R., Li, H., Dong, W.-K., Lyu, H., Li, Y., Li, J., Yu, H., et al. (2025) · Custom Integrated Circuits Conference · doi:10.1109/cicc63670.2025.10983287 · Cited by 9

Low-Power and Area-Efficient CIM: An SRAM-based fully-digital computing-in-memory hardware acceleration processor with approximate adder tree for multi-precision sparse neural networks

Fang, Z., Wang, Y., & Xu, Y. (2025) · Microelectronics Journal · doi:10.1016/j.mejo.2025.106903 · Cited by 9

Eidetic: An In-Memory Matrix Multiplication Accelerator for Neural Networks

Eckert, C. A., Subramaniyan, A. K., Wang, X., Augustine, C., Iyer, R., & Das, R. (2022) · IEEE Transactions on Computers · doi:10.1109/tc.2022.3214151 · Cited by 9

A 65-nm Digital Stochastic Compute-in-Memory CNN Processor With 8-bit Precision

Yang, J., Li, T., Romaszkan, W., Gupta, P., & Pamarti, S. (2025) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2025.3554554 · Cited by 8

A 65nm 8-bit All-Digital Stochastic-Compute-In-Memory Deep Learning Processor

Yang, J., Li, T., Romaszkan, W., Gupta, P., & Pamarti, S. (2022) · IEEE Asian Solid-State Circuits Conference (A-SSCC) · doi:10.1109/a-sscc56115.2022.9980613 · Cited by 8

Lookup Table-Based Computing-in-Memory Macro Approximating Dot Products Without Multiplications for Energy-Efficient CNN Inference

Fuketa, H. (2023) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2023.3290151 · Cited by 8

An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage

Lin, Y., Li, Y., Zhang, H., Ma, H., Lv, J., Jiang, A., Du, Y., & Du, L. (2024) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2024.3419902 · Cited by 8

Computing-in-memory with thin-filmtransistors: challenges and opportunities

Tang, W., Liu, J., Li, H., Chen, D., Jiang, C. H., Li, X., & Yang, H. (2022) · Flexible and Printed Electronics · doi:10.1088/2058-8585/ac541d · Cited by 8

WDVR-RAM: A 0.25–1.2 V, 2.6–76 POPS/W Charge-Domain In-Memory-Computing Binarized CNN Accelerator for Dynamic AIoT Workloads

Zhang, H., Shu, Y., Deng, Q., Sun, H., Zhao, W., & Ha, Y. (2023) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2023.3294296 · Cited by 8

A Customized NoC Architecture to Enable Highly Localized Computing-on-the-Move DNN Dataflow

Zhou, K., He, Y., Xiao, R., Liu, J., & Huang, K. (2021) · IEEE Transactions on Circuits & Systems II Express Briefs · doi:10.1109/tcsii.2021.3134799 · Cited by 8

A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-Normalization

Kneip, A., Lefebvre, M., Verecken, J., & Bol, D. (2022) · European Solid-State Circuits Conference (ESSCIRC) · doi:10.1109/esscirc55480.2022.9911348 · Cited by 7

29.7 CCSA: A 394TOPS/W Mixed-Signal GPS Accelerator with Charge-Based Correlation Computing for Signal Acquisition

Li, J., He, W., Zhang, B., Qi, L., He, G., & Seok, M. (2023) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc42615.2023.10067275 · Cited by 7

LineDL: Processing Images Line-by-Line With Deep Learning

Huang, Y., Chen, W., Peng, L., Liu, Y., Wang, M., Zhang, X.-P. S., & Zeng, X. (2023) · IEEE Transactions on Image Processing · doi:10.1109/tip.2023.3277394 · Cited by 8

Analog-to-Digital Converter Design for Diverse Performance Computing-in-Memory Systems: A Comprehensive Review

Xiao, S., Li, F., Hao, T., Xiao, L., Xiao, M., Mao, W., & Han, G. (2025) · Integrated Circuits and Systems · doi:10.23919/ics.2025.3571019 · Cited by 6

CV-CIM: A Hybrid Domain Xor-Derived Similarity-Aware Computation-in-Memory Supporting Cost-Volume Construction

Yue, Z., Wang, Y., Wang, H., Guo, R., Tu, F., Yang, J., Wei, S., Hu, Y., & Yin, S. (2024) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2024.3421589 · Cited by 6

An RRAM-Based Computing-in-Memory Macro With Low-Power Readout/Hold Circuits and Activation Differential Strategy for AdderNet

Qian, Z., Yan, S., Dai, Z., Guo, Z., Cong, Z., He, Y., Dou, C., Zhang, F., Yue, J., & Liu, Y. (2025) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2025.3546684 · Cited by 6

A Hierarchical-Hybrid Floating-Point Compute-in-Memory Macro Using FP-DAC and FP-ADC for Edge-AI Devices

Zhao, Y., Wang, Y., Martins, R. P., Chan, C., Yin, S., & Zhang, M. (2025) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2025.3599079 · Cited by 6

CIMFormer: A 38.9TOPS/W-8b Systolic CIM-Array Based Transformer Processor with Token-Slimmed Attention Reformulating and Principal Possibility Gathering

Guo, R., Wang, Y., Chen, X., Wang, L., Sun, H., Wei, J., Liu, L., Wei, S., Hu, Y., & Yin, S. (2023) · IEEE Asian Solid-State Circuits Conference (A-SSCC) · doi:10.1109/a-sscc58667.2023.10347930 · Cited by 6

3D-ISC: A 65nm 3D Compatible In-Sensor Computing Accelerator with Reconfigurable Tile Architecture for Real-Time DVS Data Compression

Krishnan, G., V, Nair, G. R., Oh, J., Anupreetham, A., Nalla, P. S., Hassan, A., Yeo, I., Kasichainula, K., Seo, J.-S., Seok, M., et al. (2023) · IEEE Asian Solid-State Circuits Conference (A-SSCC) · doi:10.1109/a-sscc58667.2023.10347978 · Cited by 5

A 161.6 TOPS/W Mixed-mode Computing-in-Memory Processor for Energy-Efficient Mixed-Precision Deep Neural Networks

Jo, W., Kim, S., Lee, J., Um, S., Li, Z., & Yoo, H. (2022) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas48785.2022.9938010 · Cited by 5

End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture

Bruschi, N., Tagliavini, G., Garofalo, A., Conti, F., Boybat, I., Luca Benini, C., & Rossi, D. (2023) · Design, Automation, and Test in Europe · doi:10.23919/date56975.2023.10137208 · Cited by 5

In-Network Accumulation: Extending the Role of NoC for DNN Acceleration

Tiwari, B., Yang, M., Wang, X., & Jiang, Y. (2022) · IEEE International System-on-Chip Conference (SOCC) · doi:10.1109/socc56010.2022.9908106 · Cited by 4

Scalable and Programmable Neural Network Inference Accelerator Based on In-Memory Computing

Jia, H., Ozatay, M., Tang, Y., Valavi, H., Pathak, R., Lee, J., & Verma, N. (2021) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2021.3119018 · Cited by 122

PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference

Zhang, B., Yin, S., Kim, M., Saikia, J., Kwon, S., Myung, S., Kim, H., Kim, S. J., Seo, J.-S., & Seok, M. (2022) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2022.3211290 · Cited by 80

PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference

Yin, S., Zhang, B., Kim, M., Saikia, J., Kwon, S., Myung, S., Kim, H., Kim, S. J., Seok, M., & Seo, J.-S. (2021) · Symposium on VLSI Circuits · doi:10.23919/vlsicircuits52068.2021.9492403 · Cited by 40

A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing

Jia, H., Valavi, H., Tang, Y., Zhang, J., & Verma, N. (2020) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2020.2987714 · Cited by 233

A Microprocessor implemented in 65nm CMOS with Configurable and Bit-scalable Accelerator for Programmable In-memory ComputingPreprint

Jia, H., Tang, Y., Valavi, H., Zhang, J., & Verma, N. (2018) · arXiv (Cornell University) · doi:10.48550/arxiv.1811.04047 · Cited by 14