The DOI matches its Crossref record; 2 of the 2 references it cites were found in a registry or an index.
SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation
Open accessAbstract
The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker - Spiking Neural Network architecture - is a massively parallel computer system designed to provide a cost-effective and flexible simulator for neuroscience experiments. It can model up to a billion neurons and a trillion synapses in biological real time. The basic building block is the SpiNNaker Chip Multiprocessor (CMP), which is a custom-designed globally asynchronous locally synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a lightweight, packet-switched asynchronous communications infrastructure. In this paper, we review the design requirements for its very demanding target application, the SpiNNaker micro-architecture and its implementation issues. We also evaluate the SpiNNaker CMP, which contains 100 million transistors in a 102-mm2die, provides a peak performance of 3.96 GIPS, and has a peak power consumption of 1 W when all processor cores operate at the nominal frequency of 180 MHz. SpiNNaker chips are fully operational and meet their power and performance requirements.
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Citations
Cites
Simple model of spiking neurons
Izhikevich, E. M. (2003) · IEEE Transactions on Neural Networks · doi:10.1109/tnn.2003.820440 · Cited by 4,828
SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation
Painkras, E., Plana, L. A., Garside, J., Temple, S., Davidson, S., Pepper, J., Clark, D., Patterson, C., & Furber, S. (2012) · Proceedings of the IEEE 2012 Custom Integrated Circuits Conference · doi:10.1109/cicc.2012.6330636 · Cited by 70
Self-citation
Cited by
Neuromorphic computing with multi-memristive synapses
Boybat, I., Le Gallo, M., Nandakumar, S. R., Moraitis, T., Parnell, T., Tuma, T., Rajendran, B., Leblebici, Y., Sebastian, A., & Eleftheriou, E. (2018) · Nature Communications · doi:10.1038/s41467-018-04933-y · Cited by 899
Advancing Neuromorphic Computing With Loihi: A Survey of Results and Outlook
Davies, M., Wild, A., Orchard, G., Sandamirskaya, Y., Guerra, G. A. F., Joshi, P., Plank, P., & Risbud, S. R. (2021) · Proceedings of the IEEE · doi:10.1109/jproc.2021.3067593 · Cited by 688
Large-scale neuromorphic computing systems
Furber, S. (2016) · Journal of Neural Engineering · doi:10.1088/1741-2560/13/5/051001 · Cited by 567
Self-citationNeuromorphic computing at scale
Kudithipudi, D., Schuman, C., Vineyard, C. M., Pandit, T., Merkel, C., Kubendran, R., Aimone, J. B., Orchard, G., Mayr, C., Benosman, R., et al. (2025) · Nature · doi:10.1038/s41586-024-08253-8 · Cited by 357
Self-citationPerez-Carrasco, J. A., Zhao, B., Serrano, C., Acha, B., Serrano-Gotarredona, T., Chen, S., & Linares-Barranco, B. (2013) · IEEE Transactions on Pattern Analysis and Machine Intelligence · doi:10.1109/tpami.2013.71 · Cited by 324
Metadata
- Authors
- Painkras, E., Plana, L. A., Garside, J., Temple, S., Galluppi, F., Patterson, C., Lester, D. R., Brown, A. D., & Furber, S. B.
- Venue
- IEEE Journal of Solid-State Circuits
- Published
- 2013-08
- Volume
- 48
- Issue
- 8
- Pages
- 1943-1953
- ISSN
- 0018-9200 (ISSN-L)
- 1558-173X
- OpenAlex
- W2102397476
- Cited by
- 530
- References
- 2
- FWCI
- 29.08
- Type
- journal article
- Language
- en
- Open access
- bronze
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- Painkras, E., Plana, L. A., Garside, J., Temple, S., Galluppi, F., Patterson, C., Lester, D. R., Brown, A. D., & Furber, S. B. (2013). SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation. IEEE Journal of Solid-State Circuits. https://doi.org/10.1109/jssc.2013.2259038
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