The DOI matches its Crossref record; 5 of the 5 references it cites were found in a registry or an index.
MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research
Abstract
Computer architects must determine how tomost effectively use finite computational resources whenrunning simulations to evaluate new architectural ideas.To facilitate efficient simulations with a range of benchmarkprograms, rn have developed the MinneSPEC inputset for the SPEC CPU 2000 benchmark suite. Thisnew workload allows computer architects to obtain simulationresults in a reasonable time using existing sirnulators.While the MinneSPEC workload is derived from thestandard SPEC CPU 2000 warklcad, it is a valid benchmarksuite in and of itself for simulation-based research.MinneSPEC also may be used to run Iarge numbers ofsimulations to find "sweet spots" in the evaluation parameterspace. This small number of promising designpoints subsequently may be investigated in more detailwith the full SPEC reference workload. In the processof developing the MinneSPEC datasets, we quantify itsdifferences in terms of function-level execution patterns,instruction mixes, and memory behaviors compared tothe SPEC programs when executed with the reference inputs.We find that for some programs, the MinneSPECprofiles match the SPEC reference dataset program behaviorvery closely. For other programs, however, theMinneSPEC inputs produce significantly different programbehavior. The MinneSPEC workload has been recognizedby SPEC and is distributed with Version 1.2 andhigher of the SPEC CPU 2000 benchmark suite.
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Cites
Gprof: A call graph execution profiler
Graham, S. L., Kessler, P. B., & Mckusick, M. K. (1982) · Proceedings of the 1982 SIGPLAN symposium on Compiler construction - SIGPLAN '82 · doi:10.1145/800230.806987 · Cited by 971
SPEC CPU2000: measuring CPU performance in the New Millennium
Henning, J. L. (2000) · Computer · doi:10.1109/2.869367 · Cited by 856
Measuring Computer Performance: A Practitioner's Guide
Lilja, D. J. (2000) · Cambridge University Press eBooks · doi:10.1017/cbo9780511612398 · Cited by 370
Self-citationAsim: a performance model framework
Emer, J., Ahuja, P., Borch, E., Klauser, A., Luk, C.-K., Manne, S., Mukherjee, S. S., Patil, H., Wallace, S., Binkert, N., et al. (2002) · Computer · doi:10.1109/2.982918 · Cited by 223
Minimal subset evaluation: rapid warm-up for simulated hardware state
Haskins, J. W., & Kevin Skadron, Y. (2002) · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · doi:10.1109/iccd.2001.955000 · Cited by 57
Cited by
Graphite: A distributed parallel simulator for multicores
Miller, J. E., Kasture, H., Kurian, G., Gruenwald, C., Beckmann, N., Celio, C., Eastep, J., & Agarwal, A. (2010) · HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture · doi:10.1109/hpca.2010.5416635 · Cited by 478
Cooperative Caching for Chip Multiprocessors
Chang, J., & Sohi, G. S. (2006) · ACM SIGARCH Computer Architecture News · doi:10.1145/1150019.1136509 · Cited by 355
Efficiently exploring architectural design spaces via predictive modeling
Ïpek, E., McKee, S. A., Caruana, R., de Supinski, B. R., & Schulz, M. (2006) · Proceedings of the 12th international conference on Architectural support for programming languages and operating systems · doi:10.1145/1168857.1168882 · Cited by 323
RAMP: Research Accelerator for Multiple Processors
Wawrzynek, J., Patterson, D., Oskin, M., Lu, S.-L., Kozyrakis, C., Hoe, J. C., Chiou, D., & Asanovic, K. (2007) · IEEE Micro · doi:10.1109/mm.2007.39 · Cited by 168
Metadata
- Authors
- KleinOsowski, A. J., & Lilja, D. J.
- Venue
- IEEE Computer Architecture Letters
- Published
- 2002-01
- Volume
- 1
- Issue
- 1
- Pages
- 7-7
- ISSN
- 1556-6056 (ISSN-L)
- OpenAlex
- W2131667412
- Cited by
- 360
- References
- 5
- FWCI
- 47.33
- Type
- journal article
- Language
- en
- Open access
- closed
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