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High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices
Abstract
This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/106. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA/μm were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.
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Citations
Cited by
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Large-Area Soft e-Skin: The Challenges Beyond Sensor Designs
Dahiya, R., Yogeswaran, N., Liu, F., Manjakkal, L., Burdet, E., Hayward, V., & Jörntell, H. (2019) · Proceedings of the IEEE · doi:10.1109/jproc.2019.2941366 · Cited by 309
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McClellan, C. J., Yalon, E., Smithe, K. K. H., Suryavanshi, S. V., & Pop, E. (2021) · ACS Nano · doi:10.1021/acsnano.0c09078 · Cited by 267
Gautam, R., Saxena, M., Gupta, R. S., & Gupta, M. (2013) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2013.2256912 · Cited by 55
Investigation of Sidewall High-k Interfacial Layer Effect in Gate-All-Around Structure
Ryu, D., Kim, M., Yu, J., Kim, S., Lee, J.-H., & Park, B.-G. (2020) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2020.2975255 · Cited by 40
Metadata
- Authors
- Singh, N., Agarwal, A., Bera, L. K., Liow, T. Y., Yang, R., Rustagi, S. C., Tung, C. H., Kumar, R., Lo, G. Q., Balasubramanian, N., & Kwong, D.-L.
- Venue
- IEEE Electron Device Letters
- Published
- 2006-05
- Volume
- 27
- Issue
- 5
- Pages
- 383-386
- ISSN
- 0741-3106 (ISSN-L)
- 1558-0563
- OpenAlex
- W2106998413
- Cited by
- 644
- References
- 0
- FWCI
- 38.80
- Type
- journal article
- Language
- en
- Open access
- closed
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- The paper
- Singh, N., Agarwal, A., Bera, L. K., Liow, T. Y., Yang, R., Rustagi, S. C., Tung, C. H., Kumar, R., Lo, G. Q., Balasubramanian, N., & Kwong, D.-L. (2006). High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices. IEEE Electron Device Letters. https://doi.org/10.1109/led.2006.873381
Data sources
Bibliographic data: Semantic Scholar, OpenAlex, Crossref.
Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.
