The DOI matches its Crossref record; 11 of the 11 references it cites were found in a registry or an index.
3D DRAM Design and Application to 3D Multicore Systems
Abstract
Editor's note:From a system architecture perspective, 3D technology can satisfy the high memory bandwidth demands that future multicore/manycore architectures require. This article presents a 3D DRAM architecture design and the potential for using 3D DRAM stacking for both L2 cache and main memory in 3D multicore architecture.—Yuan Xie, Pennsylvania State University
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EUVL is used to produce DRAM devices.
“EUVL is also used to produce dynamic random access memory (DRAM) devices 101 .”
From Extreme ultraviolet lithography (2024) · cites this paper as [101]
Citations
Cites
The M5 Simulator: Modeling Networked Systems
Binkert, N. L., Dreslinski, R., Hsu, L. R., et al. (2006) · IEEE Micro · doi:10.1109/mm.2006.82 · Cited by 848
Die Stacking (3D) Microarchitecture
Black, B., Pantuso, D., Reed, P., et al. (2006) · Proceedings of the ... annual International Symposium on Microarchitecture/Proceedings of the annual International Symposium on Microarchitecture · doi:10.1109/micro.2006.18 · Cited by 607
3D-Stacked Memory Architectures for Multi-core Processors
Loh, G. H. (2008) · ACM SIGARCH Computer Architecture News · doi:10.1145/1394608.1382159 · Cited by 544
Processor Design in 3D Die-Stacking Technologies
Loh, G. H., Xie, Y., & Black, B. (2007) · IEEE Micro · doi:10.1109/mm.2007.59 · Cited by 292
Bridging the Processor-Memory Performance Gapwith 3D IC Technology
Liu, C. C., Ganusov, I., Burtscher, M., & Tiwari, S. (2005) · IEEE Design & Test of Computers · doi:10.1109/mdt.2005.134 · Cited by 280
A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs
Thies, W., Chandrasekhar, V., & Amarasinghe, S. P. (2007) · Proceedings of the ... annual International Symposium on Microarchitecture/Proceedings of the annual International Symposium on Microarchitecture · doi:10.1109/micro.2007.38 · Cited by 275
Kgil, T., D'Souza, S. C., Saidi, A. G., et al. (2006) · International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) · doi:10.1145/1168857.1168873 · Cited by 189
BioBench: A Benchmark Suite of Bioinformatics Applications
Albayraktaroglu, K., Jaleel, A., Wu, X., et al. (2005) · IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) · doi:10.1109/ispass.2005.1430554 · Cited by 184
Ghosh, M., & Lee, H.-H. S. (2007) · Proceedings of the ... annual International Symposium on Microarchitecture/Proceedings of the annual International Symposium on Microarchitecture · doi:10.1109/micro.2007.13 · Cited by 148
Design Space Exploration for 3-D Cache
Tsai, Y.-F., Wang, F., Xie, Y., et al. (2008) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2007.915429 · Cited by 75
Barth, J., Reohr, W. R., Parries, P., et al. (2008) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2007.908006 · Cited by 60
Flagged first, then by citations
Research works printed but not linked: 2
- 2008, 3D Stacked DRAM/Bi-STAR Overview
- 0, CACTI An Integrated Cache and Memory Access Time Cycle Time Area Leakage and Dynamic Power Model
Cited by
Sorted by citations
Extreme ultraviolet lithography
Kazazis, D., Santaclara, J. G., van Schoot, J., Mochi, I., & Ekinci, Y. (2024) · Nature Reviews Methods Primers · doi:10.1038/s43586-024-00361-z · Cited by 149
Metadata
- Authors
- Sun, H., Liu, J., Anigundi, R. S., Zheng, N., Lu, J.-Q., Rose, K., & Zhang, T.
- Affiliations
- Xi'an Jiaotong University (CN)
- Rensselaer Polytechnic Institute (US)
- Venue
- IEEE Design & Test of Computers
- Published
- 2009-09
- Volume
- 26
- Issue
- 5
- Pages
- 36-47
- ISSN
- 0740-7475 (ISSN-L)
- OpenAlex
- W2077105843
- Cited by
- 53
- References
- 11
- Citations by year
- 2026: 2 · 2025: 2 · 2024: 2 · 2023: 1 · 2022: 2 · 2018: 1 · 2017: 4 · 2016: 1 · 2015: 5 · 2014: 5 · 2013: 6 · 2012: 9
- FWCI
- 5.82
- Type
- journal article
- Language
- en
- Open access
- closed
- Locations
- IEEE Design & Test of Computers (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › 3D IC and TSV technologies
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Physical Sciences › Computer Science › Computer Networks and Communications › Interconnection Networks and Systems
- Keywords
- 3D DRAM, memory bandwidth, L2 cache, main memory, 3D integrated circuits
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