The DOI matches its Crossref record; 22 of the 22 references it cites were found in a registry or an index.
Spike-timing-dependent learning in memristive nanodevices
Abstract
The neuromorphic paradigm is attractive for nanoscale computation because of its massive parallelism, potential scalability, and inherent defect-, fault-, and failure-tolerance. We show how to implement timing-based learning laws, such as spike-timing-dependent plasticity (STDP), in simple, memristive nanodevices, such as those constructed from certain metal oxides. Such nano-scale ldquosynapsesrdquo can be combined with CMOS ldquoneuronsrdquo to create neuromorphic hardware several orders of magnitude denser than is possible in conventional CMOS. The key ideas are: (1) to factor out two synaptic state variables to pre- and post-synaptic neurons; and (2) to separate computational communication from learning by time-division multiplexing of pulse-width-modulated signals through synapses. This approach offers the advantages of: better control over power dissipation; fewer constraints on the design of memristive materials used for nanoscale synapses; learning dynamics can be dynamically turned on or off (e.g. by attentional priming mechanisms communicated extra-synaptically); greater control over the precise form and timing of the STDP equations; the ability to implement a variety of other learning laws besides STDP; better circuit diversity since the approach allows different learning laws to be implemented in different areas of a single chip using the same memristive material for all synapses.
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“They can also be used to implement digital logic [9], synapses in neural applications [10,11], and hybrid circuits [6,12].”
From Sub-nanosecond switching of a tantalum oxide memristor (2011) · cites this paper as [10]
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Cites
Strukov, D. B., Snider, G. S., Stewart, D. R., & Williams, R. S. (2008) · Nature · doi:10.1038/nature06932 · Cited by 11,828
Self-citationMemristive devices and systems
Chua, L. O., & Kang, S. M. (1976) · Proceedings of the IEEE · doi:10.1109/proc.1976.10092 · Cited by 2,604
Synaptic Modification by Correlated Activity: Hebb's Postulate Revisited
Bi, G., & Poo, M. (2001) · Annual Review of Neuroscience · doi:10.1146/annurev.neuro.24.1.139 · Cited by 1,525
CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices
Strukov, D. B., & Likharev, K. K. (2005) · Nanotechnology · doi:10.1088/0957-4484/16/6/045 · Cited by 506
Array-based architecture for FET-based, nanoscale electronics
DeHon, A. M. (2003) · IEEE Transactions on Nanotechnology · doi:10.1109/tnano.2003.808508 · Cited by 370
Nano/CMOS architectures using a field-programmable nanowire interconnect
Snider, G. S., & Williams, R. S. (2007) · Nanotechnology · doi:10.1088/0957-4484/18/3/035204 · Cited by 364
Self-citationMolecule-Independent Electrical Switching in Pt/Organic Monolayer/Ti Devices
Stewart, D. R., Ohlberg, D. A. A., Beck, P. A., Chen, Y., Williams, R. S., Jeppesen, J. O., Nielsen, K. A., & Stoddart, J. F. (2003) · Nano Letters · doi:10.1021/nl034795u · Cited by 358
Error detecting codes, self-checking circuits and applications
Wakerly, J. F. (1978) · Cited by 345
Molecular electronics: from devices and interconnect to circuits and architecture
Stan, M. R., Franzon, P. D., Goldstein, S. C., Lach, J., & Ziegler, M. M. (2003) · Proceedings of the IEEE · doi:10.1109/jproc.2003.818327 · Cited by 275
Self-organized computation with unreliable, memristive nanodevices
Snider, G. S. (2007) · Nanotechnology · doi:10.1088/0957-4484/18/36/365202 · Cited by 264
Self-citationNonlinear circuit foundations for nanodevices, part I: the four-element torus
Chua, L. O. (2003) · Proceedings of the IEEE · doi:10.1109/jproc.2003.818319 · Cited by 263
Reliable Computation in the Presence of Noise
Hamming, R. W., Winograd, S., & Cowan, J. D. (1964) · Mathematics of Computation · doi:10.2307/2003803 · Cited by 256
Limits on the memory storage capacity of bounded synapses
Fusi, S., & Abbott, L. F. (2007) · Nature Neuroscience · doi:10.1038/nn1859 · Cited by 226
CMOS-like logic in defective, nanoscale crossbars
Snider, G. S., Kuekes, P. J., & Williams, R. S. (2004) · Nanotechnology · doi:10.1088/0957-4484/15/8/003 · Cited by 192
Self-citationDistributed ARTMAP: a neural network for fast distributed supervised learning
Carpenter, G. A., Milenova, B. L., & Noeske, B. W. (1998) · Neural Networks · doi:10.1016/s0893-6080(98)00019-7 · Cited by 151
Defect‐tolerant nanoelectronic pattern classifiers
Lee, J. H., & Likharev, K. K. (2007) · International Journal of Circuit Theory and Applications · doi:10.1002/cta.410 · Cited by 57
Coding Approaches to Fault Tolerance in Combinational and Dynamic Systems
Hadjicostis, C. N. (2002) · Springer eBooks · doi:10.1007/978-1-4615-0853-3 · Cited by 41
Global Reinforcement Learning in Neural Networks
Ma, X., & Likharev, K. K. (2007) · IEEE Transactions on Neural Networks · doi:10.1109/tnn.2006.888376 · Cited by 29
A novel highly reliable low-power nano architecture when von Neumann augments Kolmogorov
Beiu, V. C. (2004) · Application-Specific Systems, Architectures, and Processors · doi:10.1109/asap.2004.4 · Cited by 25
A novel highly reliable low-power nano architecture when von neumann augments kolmogorov
Beiu, V. C. (2004) · IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) · doi:10.1109/asap.2004.1342467 · Cited by 21
Fault-tolerant sub-lithographic design with rollback recovery
Naeimi, H., & DeHon, A. M. (2008) · Nanotechnology · doi:10.1088/0957-4484/19/11/115708 · Cited by 14
Can large fanin circuits perform reliable computations in the presence of noise?
Reischuk, R. (1997) · Lecture notes in computer science · doi:10.1007/bfb0045074 · Cited by 4
Cited by
Sorted by citations
Nanoscale Memristor Device as Synapse in Neuromorphic Systems
Jo, S. H., Chang, T., Ebong, I., Bhadviya, B. B., Mazumder, P., & Lu, W. (2010) · Nano Letters · doi:10.1021/nl904092h · Cited by 4,174
Wong, H.-S. P., Lee, H.-Y., Yu, S., Chen, Y.-S., Wu, Y., Chen, P.-S., Lee, B., Chen, F. T., & Tsai, M.-J. (2012) · Proceedings of the IEEE · doi:10.1109/jproc.2012.2190369 · Cited by 2,757
Towards spike-based machine intelligence with neuromorphic computing
Roy, K., Jaiswal, A., & Panda, P. (2019) · Nature · doi:10.1038/s41586-019-1677-2 · Cited by 2,383
“Figure 6 illustrates how in situ synaptic efficacy and synaptic plasticity can be accomplished using emerging non-volatile memristive technologies, arranged in a crossbar fashion 103,104 .”
BackgroundSynaptic electronics: materials, devices and applications
Kuzum, D., Yu, S., & Wong, H. ‐. P. (2013) · Nanotechnology · doi:10.1088/0957-4484/24/38/382001 · Cited by 1,257
Short-Term Memory to Long-Term Memory Transition in a Nanoscale Memristor
Chang, T., Jo, S.-H., & Lu, W. (2011) · ACS Nano · doi:10.1021/nn202983n · Cited by 1,058
Metadata
- Authors
- Snider, G. S.
- Affiliations
- Hewlett-Packard (United States) (US)
- Corresponding author
- Snider, Greg S.
- Venue
- 2008 IEEE International Symposium on Nanoscale Architectures
- Publisher
- IEEE
- Published
- 2008-06
- Pages
- 85-92
- OpenAlex
- W2101834447
- Cited by
- 341
- References
- 22
- Citations by year
- 2026: 4 · 2025: 3 · 2024: 8 · 2023: 9 · 2022: 12 · 2021: 11 · 2020: 12 · 2019: 19 · 2018: 14 · 2017: 24 · 2016: 17 · 2015: 30 · 2014: 24 · 2013: 46 · 2012: 43
- FWCI
- 30.31
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Ferroelectric and Negative Capacitance Devices
- Physical Sciences › Mathematics › Theoretical Computer Science › DNA and Biological Computing
- Keywords
- spike-timing-dependent plasticity, neuromorphic hardware, time-division multiplexing, pulse width modulation, power dissipation, learning law, attentional priming, fault-tolerant computing
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