The DOI matches its Crossref record; 22 of the 22 references it cites were found in a registry or an index.
Spike-timing-dependent learning in memristive nanodevices
Abstract
The neuromorphic paradigm is attractive for nanoscale computation because of its massive parallelism, potential scalability, and inherent defect-, fault-, and failure-tolerance. We show how to implement timing-based learning laws, such as spike-timing-dependent plasticity (STDP), in simple, memristive nanodevices, such as those constructed from certain metal oxides. Such nano-scale ldquosynapsesrdquo can be combined with CMOS ldquoneuronsrdquo to create neuromorphic hardware several orders of magnitude denser than is possible in conventional CMOS. The key ideas are: (1) to factor out two synaptic state variables to pre- and post-synaptic neurons; and (2) to separate computational communication from learning by time-division multiplexing of pulse-width-modulated signals through synapses. This approach offers the advantages of: better control over power dissipation; fewer constraints on the design of memristive materials used for nanoscale synapses; learning dynamics can be dynamically turned on or off (e.g. by attentional priming mechanisms communicated extra-synaptically); greater control over the precise form and timing of the STDP equations; the ability to implement a variety of other learning laws besides STDP; better circuit diversity since the approach allows different learning laws to be implemented in different areas of a single chip using the same memristive material for all synapses.
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“They can also be used to implement digital logic [9], synapses in neural applications [10,11], and hybrid circuits [6,12].”
From Sub-nanosecond switching of a tantalum oxide memristor (2011) · cites this paper as [10]
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“multiplexing (TDM) approach [37] can be used to design the shape of the spike to demonstrate the STDP behavior.”
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Sub-nanosecond switching of a tantalum oxide memristor
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If it's pinched it's a memristor
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BackgroundOn Spike-Timing-Dependent-Plasticity, Memristive Devices, and Building a Self-Learning Visual Cortex
Zamarreño-Ramos, C., Camuñas-Mesa, L. A., Pérez‐Carrasco, J. A., Masquelier, T., Serrano‐Gotarredona, T., & Linares-Barranco, B. (2011) · Frontiers in Neuroscience · doi:10.3389/fnins.2011.00026 · Cited by 564
“The physical implementation of one such Feature Map with AER CMOS neurons and a layer of memristor crossbar structure on top is shown in Figure 21B (Snider, 2008).”
BackgroundMethodInfluentialA correlated nickelate synaptic transistor
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“Even early proposals for memristor-based STDP learning implementations used artificial time-multiplexing to alternate continuously and synchronously between “performing” and “weight update” phases (Snider, 2008), thus requiring global system-wide synchronization.”
BackgroundThe Future of Memristors: Materials Engineering and Neural Networks
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“This kind of robustness to spikes’ precise timing is consistent with computational neuroscience works on STDP [32].”
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“Memristors synapses could play a major role in this field, since they also allow a direct implementation of unsu-pervised learning rules [454,455].”
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Graphene Dynamic Synapse with Modulatable Plasticity
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“A completely different type of demonstration is the conditional programming of a memristor by the integrated circuit in which it resides, which illustrates a key enabler for a reconfigurable architecture (21, 22, 25), memristor based logic (24) or an adaptive (or ‘‘synaptic’’) circuit that is able to learn (26, 27).”
BackgroundPlasticity in memristive devices for spiking neural networks
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Memristors: Devices, Models, and Applications [Scanning the Issue]
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Implementing p-bits With Embedded MTJ
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“The possibility of online memristive learning [29] or capacitive weighting [11] is left for future work.”
BackgroundEmerging non-volatile memories
Xue, C. J., Zhang, Y., Chen, Y., Sun, G., Yang, J. J., & Li, H. H. (2011) · International Conference on Hardware/Software Codesign and System Synthesis · doi:10.1145/2039370.2039420 · Cited by 193
“The potential applications range from memory to computation and from digital circuits to analog circuits, including next generation nonvolatile memory [42] [37] stateful logic operations via material implication [1] neuromorphic computing [31], and a variety of CMOS/memristor hybrid circuits [38].”
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A Memristive Nanoparticle/Organic Hybrid Synapstor for Neuroinspired Computing
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A memristive nanoparticle/organic hybrid synapstor for neuro-inspired computing.
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A Circuit-Based Learning Architecture for Multilayer Neural Networks With Memristor Bridge Synapses
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“As long as the multilayer neural network and back-propagation algorithm are implemented efficiently with hardware, they could be more powerful learning scheme than STDP. 1549-8328 © 2014 IEEE.”
BackgroundInfluentialMemristor: A New Concept in Synchronization of Coupled Neuromorphic C ircuits
VOLOS, C. K., Kyprianidis, I. M., Stouboulos, I. N., Cuautle, E. T. , & Vaidyanathan, S. V. (2015) · Journal of Engineering Science and Technology Review · doi:10.25103/jestr.082.21 · Cited by 171
A Boundary Condition-Based Approach to the Modeling of Memristor Nanostructures
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“However, it was only after the 2008 first-ever recognition of memristor behavior at the nano-scale from Hewlett-Packard (HP) engineer Williams [3], [4] that it started to receive significant attention for the large spectrum of opportunities it opens up in integrated circuit (IC) design, mostly for the realization of l…”
BackgroundSpecifications of Nanoscale Devices and Circuits for Neuromorphic Computational Systems
Rajendran, B., Liu, Y., Seo, J.-S., Gopalakrishnan, K., Chang, L., Friedman, D. J., & Ritter, M. B. (2012) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2012.2227969 · Cited by 158
“Many schemes have been proposed to implement various plasticity rules, taking into account the memory programming characteristics of novel RRAM devices [23]–[25].”
BackgroundA Hybrid CMOS-Memristor Neuromorphic Synapse
Azghadi, M. R., Linares-Barranco, B., Abbott, D., & Leong, P. H. W. (2016) · IEEE Transactions on Biomedical Circuits and Systems · doi:10.1109/tbcas.2016.2618351 · Cited by 155
An electrically modifiable synapse array of resistive switching memory
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Physical aspects of low power synapses based on phase change memory devices
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Bioinspired Programming of Memory Devices for Implementing an Inference Engine
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“Numerous other works propose implementing it directly when programming memory devices [5], [11], [13], [14], [18], [52]–[55].”
BackgroundMemristor emulator with tunable characteristic and its experimental results
Babacan, Y., Yeşil, A., & Kaçar, F. (2017) · AEU - International Journal of Electronics and Communications · doi:10.1016/j.aeue.2017.07.012 · Cited by 137
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“The STDP implementation was not direct and based on a time multiplexing approach proposed by Snider [59].”
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Liu, C., Yan, B., Yang, C., Song, L., Li, Z., Liu, B., Chen, Y., Li, H. H., Wu, Q., & Jiang, H. (2015) · ACM/IEEE Design Automation Conference (DAC) · doi:10.1145/2744769.2744783 · Cited by 131
“At single device level, typical synaptic features were demonstrated through the TiO2 material controlled by pulse width modulators [9] and the one-transistor-one-ReRAM (1T1R) structure assisted with pulse shape filters [10].”
MethodNeuromorphic Spiking Neural Networks and Their Memristor-CMOS Hardware Implementations
Camuñas-Mesa, L. A., Linares-Barranco, B., & Serrano‐Gotarredona, T. (2019) · Materials · doi:10.3390/ma12172745 · Cited by 136
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Neural Learning Circuits Utilizing Nano-Crystalline Silicon Transistors and Memristors
Cantley, K. D., Subramaniam, A., Stiegler, H. J., Chapman, R. A., & Vogel, E. M. (2012) · IEEE Transactions on Neural Networks and Learning Systems · doi:10.1109/tnnls.2012.2184801 · Cited by 121
“To date, most solutions involve pulse width or height modulation [3], [4], require extensive circuitry, and fail to mimic neurobiological systems.”
BackgroundLeveraging Memristive Systems in the Construction of Digital Logic Circuits
Rose, G. S., Rajendran, J., Manem, H., Karri, R., & Pino, R. E. (2011) · Proceedings of the IEEE · doi:10.1109/jproc.2011.2167489 · Cited by 120
Silver chalcogenide based memristor devices
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“Consequently, the memristor can be considered the electrical equivalent of a synapse [8].”
CrossNets: Neuromorphic Hybrid CMOS/Nanoelectronic Networks
Likharev, K. K. (2011) · Science of Advanced Materials · doi:10.1166/sam.2011.1177 · Cited by 115
“[44–46].”
A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks
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“Various neuromorphic circuits using single memristors to construct synapses have been presented [6]–[9].”
BackgroundMethodGeneral memristor with applications in multilayer neural networks
Wen, S.-P., Xie, X., Yan, Z., Huang, T.-W., & Zeng, Z.-G. (2018) · Neural Networks · doi:10.1016/j.neunet.2018.03.015 · Cited by 103
Building Neuromorphic Circuits with Memristive Devices
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“Timing information is encoded using the time division multiplexing (TDM) scheme which allocates events to occur at their prescribed time slots, while keeping the spike amplitude constant [69].”
MethodA compound memristive synapse model for statistical learning through STDP in spiking neural networks
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Material Memristive Device Circuits with Synaptic Plasticity: Learning and Memory
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Spike-timing dependent plasticity in a transistor-selected resistive switching memory
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“The PRE and the POST can interact through the STDP circuit according to three regimes, as previously proposed for synchronous operation of a STDP synapse [5, 6].”
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“Here, we use the voltage-controlled device, by model definition of [10], as a synapse whose weight variable is memristor conductance, g.”
MethodSynaptic electronics and neuromorphic computing
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Wang, Z., Ambrogio, S., Balatti, S., & Ielmini, D. (2015) · Frontiers in Neuroscience · doi:10.3389/fnins.2014.00438 · Cited by 93
“To this purpose, nanoscale resistive switches, or memristors, have been proposed as novel artificial synapses in neuromorphic systems (Likharev et al., 2003; Snider, 2008; Jo et al., 2010).”
BackgroundMethodAn Energy-Efficient Memristive Threshold Logic Circuit
Rajendran, J., Manem, H., Karri, R., & Rose, G. S. (2012) · IEEE Transactions on Computers · doi:10.1109/tc.2011.26 · Cited by 92
“Memristive synapses are interfaced with a CMOS neuron in [3], while memristive synapses are interfaced with resonant tunneling diodes (RTDs) for image processing in [4].”
BackgroundNanotube devices based crossbar architecture: toward neuromorphic computing
Zhao, W. S., Agnus, G., Derycke, V., Filoramo, A., Bourgoin, J. ‐., & Gamrat, C. (2010) · Nanotechnology · doi:10.1088/0957-4484/21/17/175202 · Cited by 89
Low-Power Resistive Switching Characteristic in HfO2/TiOx Bi-Layer Resistive Random-Access Memory
Ding, X., Feng, Y., Huang, P. C., Liu, L., & Kang, J. (2019) · Nanoscale Research Letters · doi:10.1186/s11671-019-2956-4 · Cited by 88
A memristor SPICE model for designing memristor circuits
Mahvash, M., & Parker, A. C. (2010) · IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) · doi:10.1109/mwscas.2010.5548803 · Cited by 87
“Applications of the memristor include implementing neuromorphic circuits using memristive nanodevices [4], [5], [6] and ultra dense nonvolatile memories.”
BackgroundMemristor emulator with spike-timing-dependent-plasticity
Babacan, Y., & Kaçar, F. (2016) · AEU - International Journal of Electronics and Communications · doi:10.1016/j.aeue.2016.12.025 · Cited by 84
A scalable neural chip with synaptic electronics using CMOS integrated memristors
Cruz-Albrecht, J., Derosier, T., & Srinivasa, N. (2013) · Nanotechnology · doi:10.1088/0957-4484/24/38/384011 · Cited by 83
“There have been recent neuromorphic systems [18, 19] that leverage this idea based on the crossbar design with memristive synapses that perform synaptic computation based on STDP [20, 21].”
MethodLow-Energy Robust Neuromorphic Computation Using Synaptic Devices
Kuzum, D., Jeyasingh, R. G. D., Yu, S., & Wong, H. ‐. P. (2012) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2012.2217146 · Cited by 80
“A spike scheme, which makes use of a communication signal [25], [26] between the pre- and postsynaptic neurons, can solve the problems mentioned earlier.”
BackgroundRobust neural logic block (NLB) based on memristor crossbar array
Chabi, D., Zhao, W. S., Querlioz, D., & Klein, J. (2011) · IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) · doi:10.1109/nanoarch.2011.5941495 · Cited by 81
“Research focused on unsupervised learning using Spike Timing Dependent Plasticity (STDP) falls into the category of long-term research [16-17].”
BackgroundObservation of two resistance switching modes in TiO2memristive devices electroformed at low current
Miao, F., Yang, J. J., Borghetti, J. L., Medeiros‐Ribeiro, G., & Williams, R. S. (2011) · Nanotechnology · doi:10.1088/0957-4484/22/25/254007 · Cited by 77
Memristive devices in computing system
Yang, J. J., & Williams, R. S. (2013) · ACM Journal on Emerging Technologies in Computing Systems · doi:10.1145/2463585.2463587 · Cited by 78
Memristor PUFs: a new generation of memory-based physically unclonable functions
Koeberl, P., Koçabas, Ü., & Sadeghi, A. (2013) · Design, Automation, and Test in Europe · doi:10.5555/2485288.2485390 · Cited by 76
Kim, Y., Zhang, Y., & Li, P. (2015) · ACM Journal on Emerging Technologies in Computing Systems · doi:10.1145/2700234 · Cited by 74
“Additionally, we propose a new digital analog PWM scheme has been conceptualized for implementing the STDP earning rule [Snider 2008], the presented digital design is more amenable to integration into a digital system architecture.”
BackgroundMethodIf It’s Pinched It’s a Memristor
Chua, L. O. (2013) · Springer eBooks · doi:10.1007/978-1-4614-9068-5_2 · Cited by 79
On neuromorphic spiking architectures for asynchronous STDP memristive systems
Pérez‐Carrasco, J. A., Zamarreño-Ramos, C., Serrano‐Gotarredona, T., & Linares-Barranco, B. (2010) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.2010.5537484 · Cited by 70
Dopant Control by Atomic Layer Deposition in Oxide Films for Memristive Switches
Yang, J. J., Kobayashi, N. P., Strachan, J. P., Zhang, M.-X., Ohlberg, D. A. A., Pickett, M. D., Li, Z., Medeiros‐Ribeiro, G., & Williams, R. S. (2010) · Chemistry of Materials · doi:10.1021/cm1020959 · Cited by 70
Evolution of Plastic Learning in Spiking Networks via Memristive Connections
Howard, G., Gale, E., Bull, L., Costello, B. D. L., & Adamatzky, A. (2012) · IEEE Transactions on Evolutionary Computation · doi:10.1109/tevc.2011.2170199 · Cited by 69
“follow [32], [42] in using discrete-time stepwise waveforms.”
MethodA digital neuromorphic VLSI architecture with memristor crossbar synaptic array for machine learning
Kim, Y., Zhang, Y., & Li, P. (2012) · IEEE International SOC Conference (SOCC) · doi:10.1109/socc.2012.6398336 · Cited by 69
“While an analog pulse width modulation (PWM) scheme has been conceptualized for implementing the STDP learning rule [10], we propose a new digital PWM scheme for both reading and STDP update of memristive synapses.”
BackgroundMethodA Proposal for Hybrid Memristor-CMOS Spiking Neuromorphic Learning Systems
Serrano‐Gotarredona, T., Prodromakis, T., & Linares-Barranco, B. (2013) · IEEE Circuits and Systems Magazine · doi:10.1109/mcas.2013.2256271 · Cited by 69
“This combination of knowledge results in the proposal of potential artificial architectures for STDP learning systems [17]–[20], [54], [55], [77].”
BackgroundBroccard, F. D., Joshi, S., Wang, J., & Cauwenberghs, G. (2017) · Journal of Neural Engineering · doi:10.1088/1741-2552/aa67a9 · Cited by 74
“Recent studies implementing learning in memristors via spike-timing-dependent plasticity further demonstrate their viability for use as synapses in VLSI neural networks [152, 153].”
MethodImitating the brain with neurocomputer a “new” way towards artificial general intelligence
Huang, T. (2017) · Machine Intelligence Research · doi:10.1007/s11633-017-1082-y · Cited by 65
Exploiting memristance in adaptive asynchronous spiking neuromorphic nanotechnology systems
Linares-Barranco, B., & Serrano‐Gotarredona, T. (2009) · DIGITAL.CSIC (Spanish National Research Council (CSIC)) · Cited by 60
Materials, technologies, and circuit concepts for nanocrossbar-based bipolar RRAM
Kügeler, C., Rosezin, R., Linn, E., Bruchhaus, R., & Waser, R. M. (2011) · Applied Physics A · doi:10.1007/s00339-011-6287-2 · Cited by 60
Compact Model of HfOX-Based Electronic Synaptic Devices for Neuromorphic Computing
Huang, P. C., Zhu, D., Chen, S., Zhou, Z., Chen, Z., Gao, B., Liu, L., Liu, X., & Kang, J. (2017) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2016.2643162 · Cited by 57
“The HfOX -based crossbar synapse network can potentially offer comparable connectivity and function density to those biological systems and operate in a way analogous to biological systems rather than digital computer [29].”
BackgroundModeling for multilevel switching in oxide-based bipolar resistive memory
Hur, J., Kim, K. M., Chang, M., Lee, S. R., Lee, D., Lee, C. B., Lee, M., Kim, Y.-B., Kim, C., & Chung, U. (2012) · Nanotechnology · doi:10.1088/0957-4484/23/22/225702 · Cited by 56
Learning with memristive devices: How should we model their behavior?
Querlioz, D., Dollfus, P., Bichler, O., & Gamrat, C. (2011) · IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) · doi:10.1109/nanoarch.2011.5941497 · Cited by 61
“It has indeed been suggested [23],[24],[25] and shown experimentally [11] that memristive devices can implement a learning rule observed in biological synapses (Spike Timing Dependent Plasticity [26]).”
BackgroundIsah, A., & Bilbault, J. (2022) · Journal of Low Power Electronics and Applications · doi:10.3390/jlpea12030044 · Cited by 57
AHaH Computing–From Metastable Switches to Attractors to Machine Learning
Nugent, M. A., & Molter, T. W. (2014) · PLoS ONE · doi:10.1371/journal.pone.0085175 · Cited by 55
“In 2008, HP Laboratories announced the production of Chua’s postulated electronic device, the memristor [48] and explored their use as synapses in neuromorphic circuits [49].”
BackgroundGiant nonvolatile resistive switching in a Mott oxide and ferroelectric hybrid
Salev, P., del Valle, J., Kalcheim, Y., & Schuller, I. K. (2019) · Proceedings of the National Academy of Sciences · doi:10.1073/pnas.1822138116 · Cited by 54
“Because a human brain contains on the order of 10(10) neurons and 10(14) synapses, the implementation of a similar-complexity machine requires the development of simple circuits using ultralow power consumption artificial neurons and synapses (7).”
BackgroundRecent advances in neuromorphic transistors for artificial perception applications
Wang, W. S., & Zhu, L. Q. (2022) · Science and Technology of Advanced Materials · doi:10.1080/14686996.2022.2152290 · Cited by 56
“dependent plasticity (STDP) learning rule in memristive devices [11].”
BackgroundAssociate learning and correcting in a memristive neural network
Chen, L., Li, C., Wang, X., & Duan, S. (2012) · Neural Computing and Applications · doi:10.1007/s00521-012-0868-7 · Cited by 53
Metadata
- Authors
- Snider, G. S.
- Affiliations
- Hewlett-Packard (United States) (US)
- Corresponding author
- Snider, Greg S.
- Venue
- 2008 IEEE International Symposium on Nanoscale Architectures
- Publisher
- IEEE
- Published
- 2008-06
- Pages
- 85-92
- OpenAlex
- W2101834447
- Cited by
- 341
- References
- 22
- Citations by year
- 2026: 4 · 2025: 3 · 2024: 8 · 2023: 9 · 2022: 12 · 2021: 11 · 2020: 12 · 2019: 19 · 2018: 14 · 2017: 24 · 2016: 17 · 2015: 30 · 2014: 24 · 2013: 46 · 2012: 43
- FWCI
- 30.31
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Ferroelectric and Negative Capacitance Devices
- Physical Sciences › Mathematics › Theoretical Computer Science › DNA and Biological Computing
- Keywords
- spike-timing-dependent plasticity, neuromorphic hardware, time-division multiplexing, pulse width modulation, power dissipation, learning law, attentional priming, fault-tolerant computing
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