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Cited by 435

The DOI matches its Crossref record; 8 of the 8 references it cites were found in a registry or an index.

Optimal interconnection circuits for VLSI

Bakoglu, H.B., Meindl, J.D.·1985·IEEE Transactions on Electron Devices

Abstract

The propagation delay of interconnection lines is a major factor in determining the performance Of VLSI circuits because the RC time delay of these lines increases rapidly as chip size is increased and cross-sectional interconnection dimensions are reduced. In this paper, a model for interconnection time delay is developed that includes the effects of scaling transistor, interconnection, and chip dimensions. The delays of aluminum, WSi2, and polysilicon lines are compared, and propagation delays in future VLSI circuits are projected. Properly scaled multilevel conductors, repeaters, cascaded drivers, and cascaded driver/ repeater combinations are investigated as potential methods for reducing propagation delay. The model yields optimal cross-sectional interconnection dimensions and driver/repeater configurations that can lower propagation delays by more than an order of magnitude in MOSFET circuits.

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Crossref · 10.1109/t-ed.1985.22046

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Metadata

Authors
Bakoglu, H. B., & Meindl, J. D.
Venue
IEEE Transactions on Electron Devices
Published
1985-05
Volume
32
Issue
5
Pages
903-909
ISSN
  • 0018-9383 (ISSN-L)
  • 1557-9646
OpenAlex
W2151817873
Cited by
435
References
8
FWCI
6.59
Type
journal article
Language
en
Open access
closed

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CoChat. (2026). Citation check: Optimal interconnection circuits for VLSI. https://app.cochat.ai/papers/10.1109/t-ed.1985.22046
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Bakoglu, H. B., & Meindl, J. D. (1985). Optimal interconnection circuits for VLSI. IEEE Transactions on Electron Devices. https://doi.org/10.1109/t-ed.1985.22046

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Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).

Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.