The DOI matches its Crossref record; 46 of the 46 references it cites were found in a registry or an index.
A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)
Open accessAbstract
Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here, we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multicore neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.
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Cites
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A million spiking-neuron integrated circuit with a scalable communication network and interface
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Dynamical Systems in Neuroscience: The Geometry of Excitability and Bursting
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NEURONAL CIRCUITS OF THE NEOCORTEX
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Cited by
Gallego, G., Delbruck, T., Orchard, G., Bartolozzi, C., Taba, B., Censi, A., Leutenegger, S., Davison, A. J., Conradt, J., Daniilidis, K., et al. (2022) · IEEE Transactions on Pattern Analysis and Machine Intelligence · doi:10.1109/tpami.2020.3008413 · Cited by 2,566
Opportunities for neuromorphic computing algorithms and applications
Schuman, C. D., Kulkarni, S. R., Parsa, M., Mitchell, J. P., Date, P., & Kay, B. (2022) · Nature Computational Science · doi:10.1038/s43588-021-00184-y · Cited by 1,117
Neuro-inspired computing chips
Zhang, W., Gao, B., Tang, J., Yao, P., Yu, S., Chang, M.-F., Yoo, H.-J., Qian, H., & Wu, H. (2020) · Nature Electronics · doi:10.1038/s41928-020-0435-7 · Cited by 892
Brain-inspired computing needs a master plan
Mehonic, A., & Kenyon, A. J. (2022) · Nature · doi:10.1038/s41586-021-04362-w · Cited by 632
Flexible Electronics and Devices as Human–Machine Interfaces for Medical Robotics
Heng, W., Solomon, S., & Gao, W. (2022) · Advanced Materials · doi:10.1002/adma.202107902 · Cited by 609
Metadata
- Authors
- Moradi, S., Qiao, N., Stefanini, F., & Indiveri, G.
- Venue
- IEEE Transactions on Biomedical Circuits and Systems
- Published
- 2018-02
- Volume
- 12
- Issue
- 1
- Pages
- 106-122
- ISSN
- 1932-4545 (ISSN-L)
- 1940-9990
- OpenAlex
- W2749476078
- Cited by
- 650
- References
- 46
- FWCI
- 18.80
- Type
- journal article
- Language
- en
- Open access
- green
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- Moradi, S., Qiao, N., Stefanini, F., & Indiveri, G. (2018). A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs). IEEE Transactions on Biomedical Circuits and Systems. https://doi.org/10.1109/tbcas.2017.2759700
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Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.
