The DOI matches its Crossref record; 8 of the 8 references it cites were found in a registry or an index.
DaDianNao: A Neural Network Supercomputer
Abstract
Many companies are deploying services largely based on machine-learning algorithms for sophisticated processing of large amounts of data, either for consumers or industry. The state-of-the-art and most popular such machine-learning algorithms are Convolutional and Deep Neural Networks (CNNs and DNNs), which are known to be computationally and memory intensive. A number of neural network accelerators have been recently proposed which can offer high computational capacity/area ratio, but which remain hampered by memory accesses. However, unlike the memory wall faced by processors on general-purpose workloads, the CNNs and DNNs memory footprint, while large, is not beyond the capability of the on-chip storage of a multi-chip system. This property, combined with the CNN/DNN algorithmic characteristics, can lead to high internal bandwidth and low external communications, which can in turn enable high-degree parallelism at a reasonable area cost. In this article, we introduce a custom multi-chip machine-learning architecture along those lines, and evaluate performance by integrating electrical and optical inter-chip interconnects separately. We show that, on a subset of the largest known neural network layers, it is possible to achieve a speedup of 656.63× over a GPU, and reduce the energy by 184.05× on average for a 64-chip system. We implement the node down to the place and route at 28 nm, containing a combination of custom storage and computational units, with electrical inter-chip interconnects.
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Zhang, Q., Zhang, M., Chen, T., Sun, Z., Ma, Y., & Yu, B. (2019) · Neurocomputing · doi:10.1016/j.neucom.2018.09.038 · Cited by 434
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Lightweight Deep Learning for Resource-Constrained Environments: A Survey
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Analyzing and Increasing the Reliability of Convolutional Neural Networks on GPUs
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Designing efficient accelerator of depthwise separable convolutional neural network on FPGA
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Metadata
- Authors
- Luo, T., Liu, S., Li, L., Wang, Y., Zhang, S., Chen, T., Xu, Z., Temam, O., & Chen, Y.
- Venue
- IEEE Transactions on Computers
- Published
- 2017-01-01
- Volume
- 66
- Issue
- 1
- Pages
- 73-88
- ISSN
- 0018-9340 (ISSN-L)
- OpenAlex
- W2522548197
- Cited by
- 175
- References
- 8
- FWCI
- 17.05
- Type
- journal article
- Language
- en
- Open access
- closed
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- Luo, T., Liu, S., Li, L., Wang, Y., Zhang, S., Chen, T., Xu, Z., Temam, O., & Chen, Y. (2017). DaDianNao: A Neural Network Supercomputer. IEEE Transactions on Computers. https://doi.org/10.1109/tc.2016.2574353
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