Cited by 72Quantum Computing Algorithms and ArchitectureQuantum Information and CryptographyVLSI and FPGA Design Techniques

Timing and Resource-Aware Mapping of Quantum Circuits to Superconducting Processors

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Lao, Lingling, van Someren, Hans, Ashraf, Imran, Almudever, Carmen G.·2022·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Abstract

Quantum algorithms need to be compiled to respect the constraints imposed by quantum processors, which is known as the mapping problem. The mapping procedure will result in an increase of the number of gates and of the circuit latency, decreasing the algorithm’s success rate. It is crucial to minimize mapping overhead, especially for noisy intermediate-scale quantum (NISQ) processors that have relatively short qubit coherence times and high gate error rates. Most of prior mapping algorithms have only considered constraints, such as the primitive gate set and qubit connectivity, but the actual gate duration and the restrictions imposed by the use of shared classical control electronics have not been taken into account. In this article, we present a mapper called Qmap to make quantum circuits executable on scalable processors with the objective of achieving the shortest circuit latency. In particular, we propose an approach to formulate the classical control restrictions as resource constraints in a conventional list scheduler with polynomial complexity. Furthermore, we implement a routing heuristic to cope with the connectivity limitation. This router finds a set of movement operations that minimally extends circuit latency. To analyze the mapping overhead and evaluate the performance of different mappers, we map 56 quantum benchmarks onto a superconducting processor named Surface-17. Compared to a prior mapping strategy that minimizes the number of operations, Qmap can reduce the latency overhead (LtyOH) up to 47.3% and operation overhead up to 28.6%, respectively.

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Crossref · 10.1109/tcad.2021.3057583

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  • The runtime of algorithms that calculate costs of all potential swapping candidates in each iteration when selecting a SWAP was very long.

    “Although the above-mentioned algorithms claimed to achieve optimal mapping solutions, the runtime of these algorithms was very long due to the fact that they needed to calculate the costs of all the potential swapping candidates in each iteration when selecting a SWAP.”
  • These algorithms could only handle mapping problems up to 50 qubits.

    “Consequently, they could only handle mapping problems up to 50 qubits, which is much smaller than the number of required qubits for achieving quantum advantage.”

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Research works printed but not linked: 12

  1. [2]R. P. Feynman, International Journal of Theoretical Physics 21 , 467 (1982).
  2. [12]A. Lye, R. Wille, and R. Drechsler, in The 20th Asia and South Pacific Design Automation Conference (ASPDAC) (IEEE, 2015) pp. 178-183.
  3. [14]A. Farghadan and N. Mohammadzadeh, International Journal of Circuit Theory and Applications 45 , 989 (2017).
  4. [20]G. Li, Y. Ding, and Y. Xie, in Proceedings of the TwentyFourth International Conference on Architectural Support for Programming Languages and Operating Systems (ACM, 2019) pp. 1001-1014. port from the Intel Corporation. LLL also acknowledges funding from the China Scholarship Council.
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  9. Annual Design Automation Conference (DAC)) (ACM, 2013) p. 42.
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Authors
Lao, L., van Someren, H., Ashraf, I., & Almudever, C. G.
Affiliations
  • QuTech (NL)
  • HITEC University (PK)
Venue
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Published
2022-02
Volume
41
Issue
2
Pages
359-371
ISSN
  • 0278-0070 (ISSN-L)
  • 1937-4151
OpenAlex
W3038380154
Cited by
72
References
55
Citations by year
2026: 7 · 2025: 15 · 2024: 18 · 2023: 13 · 2022: 7 · 2021: 8 · 2020: 4
FWCI
4.06
Type
journal article
Language
en
Open access
Locations
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (publishedVersion)
  • arXiv (Cornell University) (submittedVersion)
  • UCL Discovery (University College London) (submittedVersion)
  • Research Repository (Delft University of Technology) (submittedVersion)
  • Data Archiving and Networked Services (DANS) (submittedVersion, other-oa)
  • arXiv (Cornell University)
Funders
  • Intel Corporation
  • China Scholarship Council
Topics
  • Physical Sciences › Computer Science › Artificial Intelligence › Quantum Computing Algorithms and Architecture
  • Physical Sciences › Computer Science › Artificial Intelligence › Quantum Information and Cryptography
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › VLSI and FPGA Design Techniques
Keywords
quantum circuit mapping, superconducting quantum processors, resource-aware scheduling, list scheduling, qubit connectivity, heuristic routing, NISQ devices, quantum circuit compilation

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