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Cited by 44Semiconductor materials and devicesAdvancements in Semiconductor Devices and Circuit DesignFerroelectric and Negative Capacitance Devices

The DOI matches its Crossref record.

High Work-Function Metal Gate and High-<tex>$kappa$</tex>Dielectrics for Charge Trap Flash Memory Device Applications

Jeon, S., Han, J.H., Lee, J.H., Choi, S., Hwang, H., Kim, C.·2005·IEEE Transactions on Electron Devices
DOI 10.1109/ted.2005.859691
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Abstract

We report the impact of high work-function (/spl Phi//sub M/) metal gate and high-/spl kappa/ dielectrics on memory properties of NAND-type charge trap Flash (CTF) memory devices. In this paper, theoretical and experimental studies show that high /spl Phi//sub M/ gate and high permittivity (high-/spl kappa/) dielectrics play a key role in eliminating electron back tunneling though the blocking dielectric during the erase operation. Techniques to improve erase efficiency of CTF memory devices with a fixed metal gate by employing various chemicals and structures are introduced and those mechanisms are discussed. Though process optimization of high /spl Phi//sub M/ gate and high-/spl kappa/ materials, enhanced CTF device characteristics such as high speed, large memory window, and good reliability characteristics of the CTF devices are obtained.

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Crossref · 10.1109/ted.2005.859691

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  • The charge trap memristor mechanism is identical to charge-trap flash memory, in which reversible charge trapping and de-trapping to the charge trap layer alter the threshold voltage of the transistor.

    “The CTM mechanism is identical to the charge‐trap flash (CTF) memory, in which reversible charge trapping and de‐trapping to the charge trap layer alter the threshold voltage of the transistor.[ 14 , 15 , 16 ]”

    From Retention Secured Nonlinear and Self-Rectifying Analog Charge Trap Memristor for Energy-Efficient Neuromorphic Hardware (2023) · cites this paper as [14]

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Research works printed but not linked: 15

  1. 10.1109/55.998871 · DOI
  2. 10.1109/101.857747 · DOI
  3. 10.1109/55.852963 · DOI
  4. 10.1109/iedm.2004.1419324 · DOI
  5. Lee, A novel SONOS structure of ${\rm SiO}_{2}/{\sin}/{\rm Al}_{2}{\rm O}_{3}$ with TaN metal gate for multigiga bit Flash memories, 613
  6. 10.1109/VLSIT.1997.623724 · DOI
  7. 10.1002/0470068329 · DOI · Paper page
  8. 10.1016/S0038-1101(03)00174-6 · DOI
  9. 10.1109/LED.2002.1004227 · DOI
  10. 10.1103/PhysRevB.25.6406 · DOI
  11. 10.1109/iedm.2001.979597 · DOI
  12. Park, Thermally robust dual-work function $\hbox{ALD-MN}_{\rm x}$ MOSFET’s using conventional CMOS process flow, 186
  13. Gusev, Advanced gate stacks with fully silicided (FUSI) gates and high-$\kappa$ dielectrics: enhanced performance at reduced gate leakage, 79
  14. 10.1109/VLSIT.2004.1345471 · DOI
  15. Mayer, 1990, Electron. Mater. Sci., 169

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Metadata

Authors
Jeon, S., Han, J. H., Lee, J. H., Choi, S., Hwang, H., & Kim, C.
Affiliations
  • Samsung (South Korea) (KR)
  • Gwangju Institute of Science and Technology (KR)
ORCID
Venue
IEEE Transactions on Electron Devices
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Published
2005-12
Volume
52
Issue
12
Pages
2654-2659
ISSN
0018-9383 (ISSN-L)
DOI
10.1109/ted.2005.859691
OpenAlex
W2134330702
Cited by
44
References
0
Citations by year
2025: 2 · 2023: 3 · 2022: 2 · 2021: 2 · 2019: 1 · 2018: 2 · 2017: 2 · 2016: 3 · 2013: 4 · 2012: 1
FWCI
0.95
Type
journal article
Language
en
Open access
closed
Licence
ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html (vor)
Locations
IEEE Transactions on Electron Devices (publishedVersion)
Topics
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Semiconductor materials and devices
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Advancements in Semiconductor Devices and Circuit Design
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Ferroelectric and Negative Capacitance Devices
Keywords
charge trap flash memory, NAND flash memory, high-k dielectrics, memory window, device reliability

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