Self-Adaptive Write Circuit for Low-Power and Variation-Tolerant Memristors
Abstract
Memristive devices such as memristors that have been intensively studied for their possibilities as a strong candidate for future memories are known to have two problems. First, they need a large current in write operation, and second their process-V -temperature (PVT) variations are large compared with the conventional DRAM and FLASH memories. Moreover, the large writing current can be magnified with PVT variations. In this letter, a new write circuit is proposed to prevent unnecessary power loss by using a self-adjusting circuit for properly sizing the writing pulsewidth, thereby minimizing power consumption. The simulation results show that self-adjusting the pulsewidth can save power by 76% on average, compared to the conventional write circuit with a fixed pulsewidth.
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- Authors
- Jo, K.-H., Jung, C.-M., Min, K.-S., & Kang, S.-M.
- Affiliations
- Kookmin University (KR)
- University of California, Merced (US)
- Venue
- IEEE Transactions on Nanotechnology
- Published
- 2010-11
- Volume
- 9
- Issue
- 6
- Pages
- 675-678
- ISSN
- 1536-125X (ISSN-L)
- 1941-0085
- OpenAlex
- W2114601050
- Cited by
- 53
- References
- 16
- Citations by year
- 2026: 1 · 2024: 2 · 2023: 6 · 2022: 4 · 2021: 1 · 2020: 2 · 2019: 3 · 2018: 5 · 2017: 3 · 2016: 3 · 2015: 6 · 2014: 6 · 2013: 6 · 2012: 4
- FWCI
- 2.77
- Type
- journal article
- Language
- en
- Open access
- closed
- Locations
- IEEE Transactions on Nanotechnology (publishedVersion)
- Funders
- IC Design Education Center
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Ferroelectric and Negative Capacitance Devices
- Keywords
- memristors, low-power memory, PVT variation, variation tolerance, energy consumption reduction
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