A Ubiquitous Machine Learning Accelerator with Automatic Parallelization on FPGA
Abstract
Machine learning has been widely applied in various emerging data-intensive applications, and has to be optimized and accelerated by powerful engines to process very large scale data. Recently, the instruction set based accelerators on Field Progarmmable Gate Arrays (FPGAs) have been a promising topic for machine learning applications. The customized instructions can be further scheduled to achieve higher instruction-level parallelism. In this article, we design a ubiquitous accelerator with out-of-order automatic parallelization for large-scale data-intensive applications. The accelerator accommodates four representative applications, including clustering algorithms, deep neural networks, genome sequencing, and collaborative filtering. In order to improve the coarse-grained instruction-level parallelism, the accelerator employs an out-of-order scheduling method to enable parallel dataflow computation. We use Colored Petri Net (CPN) tools to analyze the dependences in the applications, and build a hardware prototype on the real FPGA platform. For cluster applications, the accelerator can support four different algorithms, including K-Means, SLINK, PAM, and DBSCAN. For collaborative filtering applications, it accommodates Tanimoto, euclidean, Cosine, and Pearson Correlation as Similarity metrics. For deep learning applications, we implement hardware accelerators for both training process and inference process. Finally, for genome sequencing, we design a hardware accelerator for the BWA-SW algorithm. Experimental results show that the accelerator architecture can reach up to 25X speedup against Intel processors with affordable hardware cost, insignificant power consumption, and high flexibility.
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The Ubiquitous ML Accelerator with Automatic Parallelization on FPGA uses out-of-order techniques and a 2D meshed architecture, and is able to speed up 25 times as compared to high performance Intel processors.
“By using this technique, it is able to speed up 25 times as compared to high performance intel processors, and thus it is suitable for highly intensive data processing applications.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [5]
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- Authors
- Wang, C., Gong, L., Li, X., & Zhou, X.
- Affiliations
- University of Science and Technology of China (CN)
- Venue
- IEEE Transactions on Parallel and Distributed Systems
- Published
- 2020-10-01
- Volume
- 31
- Issue
- 10
- Pages
- 2346-2359
- ISSN
- 1045-9219 (ISSN-L)
- 1558-2183
- 2161-9883
- OpenAlex
- W3020221024
- Cited by
- 37
- References
- 50
- Citations by year
- 2026: 2 · 2025: 1 · 2024: 5 · 2023: 9 · 2022: 6 · 2021: 9 · 2020: 5
- FWCI
- 6.09
- Type
- journal article
- Language
- en
- Open access
- closed
- Licence
- Locations
- IEEE Transactions on Parallel and Distributed Systems (publishedVersion)
- Funders
- National Basic Research Program of China (2017YFA0700900)
- National Natural Science Foundation of China (61976200)
- Natural Science Foundation of Jiangsu Province (BK20181193)
- Youth Innovation Promotion Association of the Chinese Academy of Sciences (2017497)
- Fundamental Research Funds for the Central Universities (WK2150110003)
- Topics
- Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
- Physical Sciences › Engineering › Electrical and Electronic Engineering › VLSI and FPGA Design Techniques
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Keywords
- machine learning accelerators, FPGA, automatic parallelization, instruction-level parallelism, customized instruction, colored Petri nets, clustering algorithms, deep neural network hardware, collaborative filtering, genome sequencing
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