The DOI matches its Crossref record; 10 of the 10 references it cites were found in a registry or an index.
The Current Sharing Optimization of Paralleled IGBTs in a Power Module Tile Using a PSpice Frequency Dependent Impedance Model
Abstract
A full circuit model of an insulated gate bipolar transistor (IGBT) power module tile is obtained using electro-magnetic analysis. A skin depth analysis on the copper and bonding wire interconnects shows that the commonly used low frequency RLC models are not adequate for power modules and reveals the necessity for a frequency dependent impedance. A method is adapted for the design of an f-dependent module tile design circuit for the first time. It is found that the importance of skin depth becomes vital especially for lower voltage ratings and faster edge rate devices as the Fourier transform becomes shifted towards higher frequencies. Analysis of the current sharing capability of the IGBTs as a function of the tile layout showed that an asymmetrical tile yields a faster response from the nearer IGBTs during inductive turn-off and an unbalanced sharing of the reverse recovery current during turn-on. A symmetric tile layout is developed. It is found that the faster current fall-time during turn-off is compensated by higher current tail oscillations thereby bringing no major improvement to the turn-off energy. During turn-on however, the reverse recovery and IGBT turn-on energy dissipation are equally distributed between the IGBTs. Simulating device imbalances also shows that threshold voltage variations have a significant effect on the current and energy sharing at turn-on whereas injection efficiency imbalances have a large influence on turn-off characteristics. The effect of device imbalances is found to decrease for a highly symmetric tile design. It is also shown that equally higher IGBT temperatures tend to improve current sharing so that IGBT module design emphasis should be placed rather on minimizing any differences in the IGBT junction temperatures. The model developed allows PSpice simulation of characteristics previously obtained only through measurements. The impact of the layout design on issues such as cross-talk, mutual inductance and ground bounce may be quickly and accurately assessed for an optimal current sharing capability.
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Metadata
- Authors
- Azar, R., Udrea, R., Ng, W. T., Dawson, F., Findlay, W., & Waind, P.
- Affiliations
- SNC-Lavalin (Canada) (CA)
- University of Cambridge (GB)
- University of Toronto (CA)
- Dynex Semiconductor (United Kingdom) (GB)
- Venue
- IEEE Transactions on Power Electronics
- Published
- 2008-01
- Volume
- 23
- Issue
- 1
- Pages
- 206-217
- ISSN
- 0885-8993 (ISSN-L)
- 1941-0107
- OpenAlex
- W2130018352
- Semantic Scholar
- 85a20f6203d29f82e5136641e2f56ef941142a19
- Cited by
- 40
- References
- 10
- Citations by year
- 2024: 3 · 2022: 2 · 2021: 2 · 2020: 3 · 2019: 3 · 2018: 2 · 2017: 3 · 2016: 1 · 2015: 4 · 2014: 3 · 2013: 3 · 2012: 3
- FWCI
- 2.19
- Type
- journal article
- Language
- en
- Open access
- closed
- Locations
- IEEE Transactions on Power Electronics (publishedVersion)
- Cambridge University Engineering Department Publications Database (submittedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Silicon Carbide Semiconductor Technologies
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Electromagnetic Compatibility and Noise Suppression
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Multilevel Inverters and Converters
- Keywords
- current sharing, skin depth, copper interconnects, bonding wires, reverse recovery current, threshold voltage variation, injection efficiency, junction temperature, electromagnetic analysis, PSpice simulation, crosstalk, ground bounce, mutual inductance
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