The DOI matches its Crossref record; 8 of the 8 references it cites were found in a registry or an index.
High-speed VLSI architectures for the AES algorithm
Abstract
This paper presents novel high-speed architectures for the hardware implementation of the Advanced Encryption Standard (AES) algorithm. Unlike previous works which rely on look-up tables to implement the SubBytes and InvSubBytes transformations of the AES algorithm, the proposed design employs combinational logic only. As a direct consequence, the unbreakable delay incurred by look-up tables in the conventional approaches is eliminated, and the advantage of subpipelining can be further explored. Furthermore, composite field arithmetic is employed to reduce the area requirements, and different implementations for the inversion in subfield GF(2/sup 4/) are compared. In addition, an efficient key expansion architecture suitable for the subpipelined round units is also presented. Using the proposed architecture, a fully subpipelined encryptor with 7 substages in each round unit can achieve a throughput of 21.56 Gbps on a Xilinx XCV1000 e-8 bg560 device in non-feedback modes, which is faster and is 79% more efficient in terms of equivalent throughput/slice than the fastest previous FPGA implementation known to date.
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Citations
Cites
A Compact Rijndael Hardware Architecture with S-Box Optimization
Satoh, A., Morioka, S., Takano, K., & Munetoh, S. (2001) · Lecture Notes in Computer Science · doi:10.1007/3-540-45682-1_15 · Cited by 683
Efficient Rijndael Encryption Implementation with Composite Field Arithmetic
Rudra, A., Dubey, P. K., Jutla, C. S., et al. (2001) · Lecture notes in computer science · doi:10.1007/3-540-44709-1_16 · Cited by 235
Standaert, F.-X., Rouvroy, G., Quisquater, J.-J., & Legat, J.-D. (2003) · Lecture Notes in Computer Science · doi:10.1007/978-3-540-45238-6_27 · Cited by 169
Implementation approaches for the Advanced Encryption Standard algorithm
Zhang, X., & Parhi, K. K. (2002) · IEEE Circuits and Systems Magazine · doi:10.1109/mcas.2002.1173133 · Cited by 152
Self-citationTwo Methods of Rijndael Implementation in Reconfigurable Hardware
Fischer, V., & Drutarovský, M. (2001) · Lecture notes in computer science · doi:10.1007/3-540-44709-1_8 · Cited by 143
Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware.
Gaj, K., & Chodowiec, P. (2000) · Cited by 142
A fully pipelined memoryless 17.8 Gbps AES-128 encryptor
Jarvinen, K. U., Tommiska, M. T., & Skyttä, J. O. (2003) · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · doi:10.1145/611817.611848 · Cited by 134
An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm
Saggese, G. P., Mazzeo, A., Mazzocca, N., & Strollo, A. G. M. (2003) · Lecture notes in computer science · doi:10.1007/978-3-540-45234-8_29 · Cited by 123
Cited by
An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA
Soltani, A., & Sharifian, S. (2015) · Microprocessors and Microsystems · doi:10.1016/j.micpro.2015.07.005 · Cited by 100
Quantum reversible circuit of AES-128
Almazrooie, M., Samsudin, A., Abdullah, R., & Mutter, K. N. (2018) · Quantum Information Processing · doi:10.1007/s11128-018-1864-3 · Cited by 75
Fault-Tolerant Encryption for Space Applications
Banu, R., & Vladimirova, T. (2009) · IEEE Transactions on Aerospace and Electronic Systems · doi:10.1109/taes.2009.4805278 · Cited by 46
Malal, A., & Tezcan, C. (2026) · Journal of Cryptographic Engineering · doi:10.1007/s13389-025-00388-2 · Cited by 4
Metadata
- Authors
- Zhang, X., & Parhi, K. K.
- Venue
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Published
- 2004-09
- Volume
- 12
- Issue
- 9
- Pages
- 957-967
- ISSN
- 1063-8210 (ISSN-L)
- 1557-9999
- OpenAlex
- W2167720990
- Cited by
- 448
- References
- 8
- FWCI
- 18.64
- Type
- journal article
- Language
- en
- Open access
- closed
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Bibliographic data: Semantic Scholar, OpenAlex, Crossref.
Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.
