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Cited by 2,376

The DOI matches its Crossref record; 21 of the 21 references it cites were found in a registry or an index.

McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures

Li, Sheng, Ahn, Jung Ho, Strong, Richard D., Brockman, Jay B., Tullsen, Dean M., Jouppi, Norman P.·2009·Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
DOI 10.1145/1669112.1669172
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Abstract

This paper introduces McPAT, an integrated power, area, and timing modeling framework that supports comprehensive design space exploration for multicore and manycore processor configurations ranging from 90nm to 22nm and beyond. At the microarchitectural level, McPAT includes models for the fundamental components of a chip multiprocessor, including in-order and out-of-order processor cores, networks-on-chip, shared caches, integrated memory controllers, and multiple-domain clocking. At the circuit and technology levels, McPAT supports critical-path timing modeling, area modeling, and dynamic, short-circuit, and leakage power modeling for each of the device types forecast in the ITRS roadmap including bulk CMOS, SOI, and double-gate transistors. McPAT has a flexible XML interface to facilitate its use with many performance simulators. Combined with a performance simulator, McPAT enables architects to consistently quantify the cost of new ideas and assess tradeoffs of different architectures using new metrics like energy-delay-area2 product (EDA2P) and energy-delay-area product (EDAP). This paper explores the interconnect options of future manycore processors by varying the degree of clustering over generations of process technologies. Clustering will bring interesting tradeoffs between area and performance because the interconnects needed to group cores into clusters incur area overhead, but many applications can make good use of them due to synergies of cache sharing. Combining power, area, and timing results of McPAT with performance simulation of PARSEC benchmarks at the 22nm technology node for both common in-order and out-of-order manycore designs shows that when die cost is not taken into account clustering 8 cores together gives the best energy-delay product, whereas when cost is taken into account configuring clusters with 4 cores gives the best EDA2P and EDAP.

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Metadata

Authors
Li, S., Ahn, J. H., Strong, R. D., Brockman, J. B., Tullsen, D. M., & Jouppi, N. P.
Venue
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Publisher
ACM
Published
2009-12-12
Pages
469-480
ISSN
1072-4451 (ISSN-L)
DOI
10.1145/1669112.1669172
OpenAlex
W2170382128
Cited by
2,376
References
21
FWCI
42.89
Type
conference paper
Language
en
Open access
closed

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CoChat. (2026). Citation check: McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures. https://app.cochat.ai/papers/10.1145/1669112.1669172
The paper
Li, S., Ahn, J. H., Strong, R. D., Brockman, J. B., Tullsen, D. M., & Jouppi, N. P. (2009). McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures. Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture. https://doi.org/10.1145/1669112.1669172

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Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).

Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.