μNAS: Constrained Neural Architecture Search for Microcontrollers
Abstract
IoT devices are powered by microcontroller units (MCUs) which are extremely resource-scarce: a typical MCU may have an underpowered processor and around 64 KB of memory and persistent storage. Designing neural networks for such a platform requires an intricate balance between keeping high predictive performance (accuracy) while achieving low memory and storage usage and inference latency. This is extremely challenging to achieve manually, so in this work, we build a neural architecture search (NAS) system, called μNAS, to automate the design of such small-yet-powerful MCU-level networks. μNAS explicitly targets the three primary aspects of resource scarcity of MCUs: the size of RAM, persistent storage and processor speed. μNAS represents a significant advance in resource-efficient models, especially for "mid-tier" MCUs with memory requirements ranging from 0.5 KB to 64 KB. We show that on a variety of image classification datasets μNAS is able to (a) improve top-1 classification accuracy by up to 4.8%, or (b) reduce memory footprint by 4-13×, or (c) reduce the number of multiply-accumulate operations by at least 2×, compared to existing MCU specialist literature and resource-efficient models. μNAS is freely available for download at https://github.com/eliberis/uNAS
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Liberis et al. (2021) presented the lNAS architecture to deploy a neural network into a KB-sized RAM for IoT-based microcontrollers.
“A recent work presents the lNAS architecture to deploy a neural network into a KB-sized RAM for the IoT-based microcontrollers (Liberis et al., 2021).”
From A review on TinyML: State-of-the-art and prospects (2022) · cites this paper as Liberis et al., 2021
The lNAS architecture allows automating neural architecture search for tiny devices while balancing accuracy and resource utilization.
“Leveraged architecture allows to automate the neural architecture search for tiny devices while balancing the accuracy and resource utilization.”
From A review on TinyML: State-of-the-art and prospects (2022) · cites this paper as Liberis et al., 2021
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Hardware Aware NAS for Optimized Embedded Texture Classification in Multisensory Glove
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Short Paper: Towards Real-Time ECG and EMG Modeling on μNPUs
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- Authors
- Liberis, E., Dudziak, Ł., & Lane, N. D.
- Affiliations
- University of Cambridge (GB)
- Samsung AI Centre Cambridge, Cambridge, United Kingdom
- Venue
- Proceedings of the 1st Workshop on Machine Learning and Systems
- Publisher
- ACM
- Published
- 2021-04-26
- Pages
- 70-79
- OpenAlex
- W3160945783
- Cited by
- 90
- References
- 12
- Citations by year
- 2026: 14 · 2025: 17 · 2024: 16 · 2023: 22 · 2022: 12 · 2021: 8 · 2020: 1
- FWCI
- 4.74
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- Workshop on Machine Learning and Systems (EuroMLSys) (publishedVersion)
- Funders
- EPSRC (EP/M50659X/1)
- European Research Council via the REDIAL project (805194)
- EPSRC (MOA Proj) (EP/S001530/1)
- Topics
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Computer Science › Computer Networks and Communications › IoT and Edge/Fog Computing
- Physical Sciences › Computer Science › Artificial Intelligence › Machine Learning and Data Classification
- Keywords
- neural architecture search, microcontroller, IoT devices, memory footprint reduction, inference latency, image classification, multiply-accumulate operations, Muna
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