Anders, Mark A.

2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors

Mathew, S. K., Srinivasan, S., Anders, M. A., Kaul, H., Hsu, S. K., Sheikh, F., Agarwal, A., Satpathy, S., & Krishnamurthy, R. K. (2012) · IEEE Journal of Solid-State Circuits

Physical Unclonable Functions (PUFs) and Hardware SecurityLow-power high-performance VLSI design

Cited by 195

An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS

Satpathy, S. K., Mathew, S. K., Kumar, R., Suresh, V., Anders, M. A., Kaul, H., Agarwal, A., Hsu, S., Krishnamurthy, R. K., & De, V. (2019) · IEEE Journal of Solid-State Circuits

Physical Unclonable Functions (PUFs) and Hardware SecurityLow-power high-performance VLSI design

Cited by 114

$\mu $ RNG: A 300–950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS

Mathew, S. K., Johnston, D., Satpathy, S., Suresh, V., Newman, P., Anders, M. A., Kaul, H., Agarwal, A., Hsu, S. K., Chen, G., et al. (2016) · IEEE Journal of Solid-State Circuits

Physical Unclonable Functions (PUFs) and Hardware SecurityLow-power high-performance VLSI design

Cited by 102

2.4GHz 7mW all-digital PVT-variation tolerant True Random Number Generator in 45nm CMOS

Srinivasan, S., Mathew, S., Ramanarayanan, R., Sheikh, F., Anders, M., Kaul, H., Erraguntla, V., Krishnamurthy, R., & Taylor, G. (2010) · 2010 Symposium on VLSI Circuits

Physical Unclonable Functions (PUFs) and Hardware SecurityLow-power high-performance VLSI design

Cited by 52