Khwa, Win-San

15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications

Dong, Q., Sinangil, M. E., Erbagci, B., Sun, D., Khwa, W.-S., Liao, H.-J., Wang, Y., & Chang, J. (2020) · 2020 IEEE International Solid- State Circuits Conference - (ISSCC)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 346

A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors

Khwa, W.-S., Chen, J.-J., Li, J.-F., Si, X., Yang, E.-Y., Sun, X., Liu, R., Chen, P.-Y., Li, Q., Yu, S., et al. (2018) · 2018 IEEE International Solid - State Circuits Conference - (ISSCC)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 260

16.1 A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices

Xue, C.-X., Hung, J.-M., Kao, H.-Y., Huang, Y.-H., Huang, S.-P., Chang, F.-C., Chen, P., Liu, T.-W., Jhang, C.-J., Su, C.-I., et al. (2021) · 2021 IEEE International Solid- State Circuits Conference (ISSCC)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 182

Fusion of memristor and digital compute-in-memory processing for energy-efficient edge computing

Wen, T.-H., Hung, J.-M., Huang, W.-H., Jhang, C.-J., Lo, Y.-C., Hsu, H.-H., Ke, Z.-E., Chen, Y.-C., Chin, Y.-H., Su, C.-I., et al. (2024) · Science

Advanced Memory and Neural ComputingParallel Computing and Optimization Techniques

Cited by 131

An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices

Hung, J.-M., Huang, Y.-H., Huang, S.-P., Chang, F.-C., Wen, T.-H., Su, C.-I., Khwa, W.-S., Lo, C.-C., Liu, R.-S., Hsieh, C.-C., et al. (2022) · 2022 IEEE International Solid- State Circuits Conference (ISSCC)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 125

A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices

Khwa, W.-S., Chiu, Y.-C., Jhang, C.-J., Huang, S.-P., Lee, C.-Y., Wen, T.-H., Chang, F.-C., Yu, S.-M., Lee, T.-Y., & Chang, M.-F. (2022) · 2022 IEEE International Solid- State Circuits Conference (ISSCC)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 125

29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification

Yoon, J.-H., Chang, M., Khwa, W.-S., Chih, Y.-D., Chang, M.-F., & Raychowdhury, A. (2021) · 2021 IEEE International Solid- State Circuits Conference (ISSCC)

Advanced Memory and Neural ComputingFerroelectric and Negative Capacitance Devices

Cited by 86