The DOI matches its Crossref record; 1 of the 1 references it cites were found in a registry or an index.
29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification
Abstract
As memory-centric workloads (AI, graph-analytics) continue to gain momentum, technology solutions that provide higher on-die memory capacity/bandwidth can provide scalability beyond SRAM. Resistive RAM (RRAM) owing to (1) higher bit-density (2-4× of SRAM), (2) CMOS process/voltage compatibility, (3) nano-second read (RD) and (4) non-volatility has emerged as a promising candidate [1]. In spite of early prototypes, several technology challenges remain, and need to be addressed through circuit-technology co-design [1]. This paper presents a 64Kb RRAM macro supporting: (1) a programmable (1 to 9) number of row-accesses (N) to enable vector-matrix multiplication (referred to as compute-in-memory, or CIM) for a target algorithm-level inference-accuracy [2] -[8], (2) voltage-based RD with active feedback, advancing the state-of-the-art current-based RD, targeted for the low ratio between the high-resistance-state (HRS) and low-resistance-state (LRS) in typical RRAM, (3) RD-disturb tolerance under RRAM drift, through embedded RD-disturb monitor and write (WR)-back and (4) in-situ WR verification to enable a tight resistance distribution.
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Most compute-in-memory or near-memory approaches based on SRAMs and digital compute do not address the energy and time costs of reloading weights, making direct side-by-side comparisons against NVM-based weight-stationary approaches difficult; several NVM compute-in-memory studies have focused on the macro-level without accounting for data transport, control or chip infrastructure costs, and are,
“Although several compute-in-memory or near-memory approaches based on SRAMs and digital compute35–38 have been presented in the literature, most of these do not address the energy and time costs of reloading weights, thus making direct side-by-side comparisons against NVM-based weight-stationary approaches difficult.”
From An analog-AI chip for energy-efficient speech recognition and transcription (2023) · cites this paper as [39]
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Xue, C.-X., Huang, T.-Y., Liu, J.-S., Chang, T.-W., Kao, H.-Y., Wang, J.-H., Liu, T.-W., Wei, S.-Y., Huang, S.-P., Wei, W.-C., et al. (2020) · 2020 IEEE International Solid- State Circuits Conference - (ISSCC) · doi:10.1109/isscc19947.2020.9063078 · Cited by 230 · cited 1×
“SS CC This paper presents a 64Kb RRAM macro supporting: (1) a programmable (1 to 9) number of row-accesses (N) to enable vector-matrix multiplication (referred to as compute-in-memory, or CIM) for a target algorithm-level inference-accuracy [2-8], (2) voltage-based RD with active feedback,…”
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An analog-AI chip for energy-efficient speech recognition and transcription
Ambrogio, S., Narayanan, P., Okazaki, A., Fasoli, A., Mackin, C., Hosokawa, K., Nomura, A., Yasuda, T., Chen, A., Friz, A., et al. (2023) · Nature · doi:10.1038/s41586-023-06337-5 · Cited by 269
“However, several NVM compute-in-memory studies have focused on the macro-level 32,34,39,40,41 , without accounting for data transport, control or chip infrastructure (such as clocking) costs.”
BackgroundHung, J.-M., Huang, Y.-H., Huang, S.-P., Chang, F.-C., Wen, T.-H., Su, C.-I., Khwa, W.-S., Lo, C.-C., Liu, R.-S., Hsieh, C.-C., et al. (2022) · 2022 IEEE International Solid- State Circuits Conference (ISSCC) · doi:10.1109/isscc42614.2022.9731715 · Cited by 125
Self-citationKhwa, W.-S., Chiu, Y.-C., Jhang, C.-J., Huang, S.-P., Lee, C.-Y., Wen, T.-H., Chang, F.-C., Yu, S.-M., Lee, T.-Y., & Chang, M.-F. (2022) · 2022 IEEE International Solid- State Circuits Conference (ISSCC) · doi:10.1109/isscc42614.2022.9731670 · Cited by 125
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Metadata
- Authors
- Yoon, J.-H., Chang, M., Khwa, W.-S., Chih, Y.-D., Chang, M.-F., & Raychowdhury, A.
- Affiliations
- Georgia Institute of Technology (US)
- Taiwan Semiconductor Manufacturing Company (Taiwan) (TW)
- Venue
- 2021 IEEE International Solid- State Circuits Conference (ISSCC)
- Publisher
- IEEE
- Published
- 2021-02-13
- Pages
- 404-406
- ISSN
- 0193-6530 (ISSN-L)
- OpenAlex
- W3135839634
- Cited by
- 86
- References
- 1
- Citations by year
- 2026: 3 · 2025: 13 · 2024: 15 · 2023: 16 · 2022: 29 · 2021: 10
- FWCI
- 27.47
- Type
- conference paper
- Language
- en
- Open access
- closed
- Licence
- Locations
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference (publishedVersion)
- Funders
- Semiconductor Research Corporation
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Ferroelectric and Negative Capacitance Devices
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Keywords
- resistive random access memory, in-memory computing, write-back, memory-centric computing, matrix-vector multiplication, 40-nm CMOS, resistance distribution
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