CoNNa–Hardware accelerator for compressed convolutional neural networks
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CoNNA's power consumption is reduced significantly although it stores feature maps in external memory.
“CoNNA's power consumption is reduced significantly although CoNNA stores feature maps in the external memory, but these consist of a cache line to store temporary data and reduce the data transfer between the accelerator and the external memory [18].”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [18]
CoNNA is able to utilize the compressed CNN technique to excel the FPGA performance as compared to the traditional standard CNN method in GPU.
“In conclusion, CoNNA is able to utilize the compressed CNN technique to excel the FPGA performance as compared to the traditional standard CNN method in GPU.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [18]
CoNNA, a hardware accelerator for compressed CNN, is able to speed up at least 3.08 times and up to 14.1 times faster than the MIT Eyeriss Accelerator.
“Based on the analysis of the research, CoNNA is able to speed up at least 3.08 times and up to 14.1 times faster than the MIT Eyeriss Accelerator [20].”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [18]
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Self-citation
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RetractedStriping input feature map cache for reducing off-chip memory traffic in CNN accelerators
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A Hybrid Deep Learning Model for Comprehensive Higher Education Quality Evaluation
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- Authors
- Struharik, R. J. R., Vukobratović, B. Z., Erdeljan, A. M., & Rakanović, D. M.
- Affiliations
- University of Novi Sad (RS)
- Corresponding author
- Struharik, Rastislav J.R.
- Venue
- Microprocessors and Microsystems
- Publisher
- Elsevier BV
- Published
- 2020-03
- Volume
- 73
- Pages
- 102991
- ISSN
- 0141-9331 (ISSN-L)
- OpenAlex
- W3000381096
- Cited by
- 18
- References
- 67
- Citations by year
- 2025: 3 · 2023: 3 · 2022: 2 · 2021: 4 · 2020: 6
- FWCI
- 1.46
- Type
- journal article
- Language
- en
- Open access
- closed
- Licence
- Locations
- Microprocessors and Microsystems (publishedVersion)
- Topics
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Keywords
- network pruning, quantization, coarse-grained reconfigurable architecture, dynamic reconfiguration, FPGA implementation, Xilinx Zynq UltraScale+, dynamic topology, feature map compression
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