Software-Hardware Codesign for Efficient Neural Network Acceleration
Abstract
Designers making deep learning computing more efficient cannot rely solely on hardware. Incorporating software-optimization techniques such as model compression leads to significant power savings and performance improvement. This article provides an overview of DeePhi's technology flow, including compression, compilation, and hardware acceleration. Two accelerators, named Aristotle and Descartes, are designed to achieve extremely high energy efficiency for both client and datacenter applications with convolutional neural network and recurrent neural network, respectively.
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Works [2] and [3] rely on centralized learning solutions that have limited scalability and privacy-preservation.
“Works in [2] and [3] rely on centralized learning solutions that have limited scalability and privacy-preservation.”
From Federated Learning for Edge Networks: Resource Optimization and Incentive Mechanism (2020) · cites this paper as [3]
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Federated Learning for Edge Networks: Resource Optimization and Incentive Mechanism
Khan, L. U., Pandey, S. R., Tran, N. H., Saad, W., Han, Z., Nguyen, M. N. H., & Hong, C. S. (2020) · IEEE Communications Magazine · doi:10.1109/mcom.001.1900649 · Cited by 506 · see citing works
“Therefore, there is a need to jointly consider both hardware design space and neural architecture search space for a more flexible design of the end device for FL [12].”
BackgroundGao, C., Neil, D., Ceolini, E., Liu, S., & Delbrück, T. (2018) · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · doi:10.1145/3174243.3174261 · Cited by 134 · see citing works
“The server- or desktop-targeted Titan X consumes about 200 W and achieves a power efficiency around 5GOp/s/W in inference of an LSTM layer with 1024 neurons [12].”
BackgroundDave, S., Baghdadi, R., Nowatzki, T., Avancha, S., Shrivastava, A., & Li, B. (2021) · Proceedings of the IEEE · doi:10.1109/jproc.2021.3098483 · Cited by 110 · see citing works
“COO [152], [153] COO-1D [101], [109], [147], [148], [158], [161], [165], [167] RLC [34], [95]–[97], [132], [145], [188] Bitmap [57], [62], [110], [132], [144], [146], [149]–[151], [153]–[155], [157] CSR [45] CSC [45], [61], [63], [102], [156], [160], [189] CSF [152]”
FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
Zhang, Y., Pan, J., Liu, X., Chen, H., Chen, D., & Zhang, Z. (2021) · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · doi:10.1145/3431920.3439296 · Cited by 112 · see citing works
“As another approach, algorithm-hardware co-design method is leveraged to develop hardware-efficient networks with fewer bits in weights and activations [14, 16, 24, 47, 49, 51].”
MethodYang, Y., Huang, Q., Wu, B., Zhang, T., Ma, L., Gambardella, G., Blott, M., Lavagno, L., Vissers, K., Wawrzynek, J., et al. (2019) · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · doi:10.1145/3289602.3293902 · Cited by 117 · see citing works
“[39, 41, 42] have achieved high frame rate on smaller devices, however, the accuracy of their network is not on par with [40] for ImageNet classification.”
BackgroundResultInfluentialDecentral and Incentivized Federated Learning Frameworks: A Systematic Literature Review
Witt, L., Heyer, M., Toyoda, K., Samek, W., & Li, D. (2022) · IEEE Internet of Things Journal · doi:10.1109/jiot.2022.3231363 · Cited by 101 · see citing works
Binary CorNET: Accelerator for HR Estimation From Wrist-PPG
Rocha, L. M. G., Biswas, D., Verhoef, B.-E., Bampi, S., Hoof, C. A. V., Konijnenburg, M., Verhelst, M., & Helleputte, N. V. (2020) · IEEE Transactions on Biomedical Circuits and Systems · doi:10.1109/tbcas.2020.3001675 · Cited by 57 · see citing works
Low-precision Floating-point Arithmetic for High-performance FPGA-based CNN Acceleration
Wu, C. H., Wang, M., Chu, X., Wang, K., & He, L. (2021) · ACM Transactions on Reconfigurable Technology and Systems · doi:10.1145/3474597 · Cited by 59 · see citing works
Uncertainty-aware Decisions in Cloud Computing
Kabir, H. M. D., Khosravi, A., Mondal, S. K., Rahman, M. M., Nahavandi, S., & Buyya, R. (2021) · ACM Computing Surveys · doi:10.1145/3447583 · Cited by 53 · see citing works
“Some applications such as neural network training can be performed efficiently with different architectures [181, 182].”
BackgroundWarehouse-scale video acceleration: co-design and deployment in the wild
Ranganathan, P., Stodolsky, D., Calow, J., Dorfman, J., Guevara, M., Smullen, C. W., IV, Kuusela, A., Balasubramanian, R., Bhatia, S., Chauhan, P., et al. (2021) · International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) · doi:10.1145/3445814.3446723 · Cited by 43 · see citing works
Adaptation of Convolution and Batch Normalization Layer for CNN Implementation on FPGA
Sledević, T. (2019) · Open Conference of Electrical, Electronic and Information Sciences (eStream) · doi:10.1109/estream.2019.8732160 · Cited by 37 · see citing works
HAO: Hardware-aware Neural Architecture Optimization for Efficient Inference
Dong, Z., Gao, Y., Huang, Q., Wawrzynek, J., So, H. K., & Keutzer, K. (2021) · IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) · doi:10.1109/fccm51124.2021.00014 · Cited by 40 · see citing works
“[13], [23], [31], [35] are manually designed solutions.”
Machine Learning and Its Applications in Studying the Geographical Distribution of Ants
Chen, S., & Ding, Y. (2022) · Diversity · doi:10.3390/d14090706 · Cited by 36 · see citing works
Real-time object detection towards high power efficiency
Yu, J., Guo, K., Hu, Y., Ning, X., Qiu, J., Mao, H., Yao, S., Tang, T., Li, B., Wang, Y., et al. (2018) · Design, Automation, and Test in Europe · doi:10.23919/date.2018.8342100 · Cited by 27 · see citing works
“Furthermore, we develop an instruction set to support different object detection algorithms on the same hardware [4], tracking the upgrade of detection framworks [6], [7].”
BackgroundMethodSelf-citationReal-Time Object Detection and Semantic Segmentation Hardware System with Deep Learning Networks
Fang, S., Tian, L., Wang, J., et al. (2018) · International Conference on Field-Programmable Technology (FPT) · doi:10.1109/fpt.2018.00081 · Cited by 24 · see citing works
“To build a high energy efficient system, software-hardware codesign should be considered [10,11,12].”
Self-citationClassification of Heart Disease from MRI Images Using Convolutional Neural Network
Sharma, A. K., Kumar, R., & Jaiswal, V. K. (2021) · International Conference on Signal Processing, Computing and Control (ISPCC) · doi:10.1109/ispcc53510.2021.9609408 · Cited by 23 · see citing works
Игоревич, А. В., Tominov, R. V., Vakulov, Z., Zhavoronkov, L. G., & Smirnov, V. A. (2023) · Nano Research · doi:10.1007/s12274-023-5639-5 · Cited by 24 · see citing works
Design of a MAGLEV System with PID Based Fuzzy Control Using CS Algorithm
Ataşlar‐Ayyıldız, B., & Karahan, O. (2020) · Cybernetics and Information Technologies · doi:10.2478/cait-2020-0037 · Cited by 23 · see citing works
Instruction Driven Cross-layer CNN Accelerator for Fast Detection on FPGA
Yu, J., Ge, G., Hu, Y., Ning, X., Qiu, J., Guo, K., Wang, Y., & Yang, H. (2018) · ACM Transactions on Reconfigurable Technology and Systems · doi:10.1145/3283452 · Cited by 21 · see citing works
“Moreover, the high latency and low bandwidth of DDR access limits the utilization rate of the computation units [11], because the computation units may stay idle waiting for the data transferred from DDR.”
BackgroundSelf-citationBlott, M., Halder, L., Leeser, M. E., & Doyle, L. (2019) · ACM Journal on Emerging Technologies in Computing Systems · doi:10.1145/3358700 · Cited by 22 · see citing works
“Within machine learning, software and hardware co-design are compulsory [29] for energy constrained compute environments.”
BackgroundMulti-task ADAS system on FPGA
Peng, J., Tian, L., Jia, X., et al. (2019) · IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) · doi:10.1109/aicas.2019.8771615 · Cited by 21 · see citing works
Self-citationDeep Neural Network Model and FPGA Accelerator Co-Design: Opportunities and Challenges
Hao, C., & Chen, D. (2018) · 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) · doi:10.1109/icsict.2018.8564956 · Cited by 19 · see citing works
“One recent paper [1] pointed out that algorithm researchers and hardware developers should work together to achieve higher efficiency of DNN computation, but did not talk about specific approaches.”
BackgroundCoNNa–Hardware accelerator for compressed convolutional neural networks
Struharik, R. J. R., Vukobratović, B. Z., Erdeljan, A. M., & Rakanović, D. M. (2020) · Microprocessors and Microsystems · doi:10.1016/j.micpro.2020.102991 · Cited by 18 · see citing works
FPGA based neural network accelerators
Kim, J.-Y. (2020) · Advances in computers · doi:10.1016/bs.adcom.2020.11.002 · Cited by 18 · see citing works
mNet2FPGA: A Design Flow for Mapping a Fixed-Point CNN to Zynq SoC FPGA
Sledević, T., & Serackis, A. (2020) · Electronics · doi:10.3390/electronics9111823 · Cited by 17 · see citing works
“This includes network training with normalized batches of data [4], the binarization of convolutional kernels [1,5,6], network compression using adaptive quantization schemes [7–10] and reducing a number of operations in the CNN model with neuromorphic techniques [11,12].”
MethodA Cryogenic Artificial Synapse based on Superconducting Memristor
Islam, M. M., Alam, S., Udoy, M. R. I., et al. (2023) · ACM Great Lakes Symposium on VLSI (GLSVLSI) · doi:10.1145/3583781.3590203 · Cited by 15 · see citing works
3D Capsule Networks for Object Classification With Weight Pruning
Kakillioglu, B., Ren, A., Wang, Y., & Velipasalar, S. (2020) · IEEE Access · doi:10.1109/access.2020.2971950 · Cited by 14 · see citing works
“NETWORK OPTIMIZATION As mentioned in Section II, it has been shown in prior work that there is significant redundancy in CNNs, and pruning, which reduces the number of weights in neural networks, has been extensively studied [12], [13], [34].”
BackgroundSelf-citationThree-Dimensional Neuromorphic Computing System With Two-Layer and Low-Variation Memristive Synapses
An, H., Al-Mamun, M. S., Orlowski, M. K., et al. (2021) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2021.3061481 · Cited by 14 · see citing works
Sledević, T., Serackis, A., & Plonis, D. (2022) · Agriculture · doi:10.3390/agriculture12111849 · Cited by 14 · see citing works
Liu, M., Yin, M., Han, K., et al. (2023) · Internet of Things · doi:10.1016/j.iot.2023.100680 · Cited by 14 · see citing works
Choi, W., Choi, K., & Park, J. (2018) · IEEE Access · doi:10.1109/access.2018.2816019 · Cited by 13 · see citing works
Towards An FPGA-targeted Hardware/Software Co-design Framework for CNN-based Edge Computing
Pham‐Quoc, C., Nguyen, X.-Q., & Thinh, T. N. (2022) · Mobile Networks and Applications · doi:10.1007/s11036-022-01985-9 · Cited by 13 · see citing works
“FPGA-based Aristotle architecture for accelerating CNNs was introduced by K.Guo et al. [14].”
MethodAnomaly Detection Using XGBoost Ensemble of Deep Neural Network Models
Thaseen, I. S., Cherukuri, A. K., Poorva, B., et al. (2021) · Cybernetics and Information Technologies · doi:10.2478/cait-2021-0037 · Cited by 11 · see citing works
Siddique, M. A. B., Zhang, Y., & An, H. (2023) · Frontiers in Computational Neuroscience · doi:10.3389/fncom.2023.1274575 · Cited by 11 · see citing works
Real-time HR Estimation from wrist PPG using Binary LSTMs
Rocha, L. M. G., Liu, M., Biswas, D., Verhoef, B.-E., Bampi, S., Kim, C. H., Hoof, C. A. V., Konijnenburg, M., Verhelst, M., & Helleputte, N. V. (2019) · IEEE Biomedical Circuits and Systems Conference (BioCAS) · doi:10.1109/biocas.2019.8918726 · Cited by 12 · see citing works
“[10] [11] Proposed”
Huang, P., Wang, C., Liu, W., et al. (2021) · IEEE Open Journal of the Computer Society · doi:10.1109/ojcs.2021.3051643 · Cited by 11 · see citing works
“Therefore, hardware/software (HW/SW) co-design [5], [20], [21] must be considered to change the abstractions and relationships between hardware and software for a trade-off between accuracy and efficiency.”
BackgroundRen, A., Zhang, T., Ye, S., Li, J., Xu, W., Qian, X., Lin, X., & Wang, Y. (2018) · arXiv (Cornell University) · doi:10.48550/arxiv.1812.11677 · Cited by 11 · see citing works
“The observation is validated by prior work [18, 20, 21] (although many are on clustering instead of quantization), and in our own investigations.”
BackgroundSelf-citationAnalog Spiking Neural Network Synthesis for the MNIST
Soupizet, T., Jouni, Z., Wang, S., Benlarbi‐Delaï, A., & Ferreira, P. M. (2023) · Journal of Integrated Circuits and Systems · doi:10.29292/jics.v18i1.663 · Cited by 11 · see citing works
“This leads by induction to the property of FNNs [28]”
BackgroundInfluentialImplementation of Yolo-v2 Image Recognition and Other Testbenches for a CNN Accelerator
Kim, C., Kim, H. M., Lyuh, C., et al. (2019) · International Conference on Consumer Electronics · doi:10.1109/icce-berlin47944.2019.8966213 · Cited by 10 · see citing works
“Two notables of them are Google’s TPU[2] which uses systolic array and DeePhi’s Aristotle[3] which processes sparse matrix calculation with multiple PEs sharing the calculation load.”
MethodEfficient Deep Neural NetworksPreprint
Wu, B. (2019) · arXiv (Cornell University) · doi:10.48550/arxiv.1908.08926 · Cited by 11 · see citing works
“The only previous work that comes close to our accuracy is [42], but its frame rate is 11.”
BackgroundDeep Learning in Reconfigurable Hardware: A Survey
Dias, M. A., & Ferreira, D. A. P. (2019) · IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum · doi:10.1109/ipdpsw.2019.00026 · Cited by 9 · see citing works
“Hardware/Software co-design is a well known solution for complex systems and good results using this technique were achieved in [11] [12] [21] [27] [31] [40], when processors”
BackgroundMethodTang, S.-N., & Han, Y.-S. (2020) · IEEE Access · doi:10.1109/access.2020.3040366 · Cited by 8 · see citing works
“When an inference operation is executed using HW acceleration at the edge end, a device that uses a software (SW)–HW codesign scheme [33]–[35] is often employed, which is developed by evaluating the work division.”
MethodA Marr's Three‐Level Analytical Framework for Neuromorphic Electronic Systems
Guo, Y., Zou, X., Hu, Y., Yang, Y., Wang, X., He, Y., Kong, R., Guo, Y., Li, G., Zhang, W., et al. (2021) · Advanced Intelligent Systems · doi:10.1002/aisy.202100054 · Cited by 10 · see citing works
Deep Neural Network Feasibility Using Analog Spiking Neurons
Soupizet, T., Jouni, Z., Sulzbach, J. F., et al. (2022) · SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) · doi:10.1109/sbcci55532.2022.9893216 · Cited by 7 · see citing works
“F k can thus be expressed as a matrix product of F k − 1 , where This leads by induction to the property of FNNs [5] The output F N of the FNN is given by a linear combination of the input I 1 .”
BackgroundMethodRRAM Based Buffer Design for Energy Efficient CNN Accelerator
Guo, K., Yu, J., Ning, X., Hu, Y., Wang, Y., & Yang, H. (2018) · IEEE Computer Society Annual Symposium on VLSI · doi:10.1109/isvlsi.2018.00085 · Cited by 7 · see citing works
“Experimental results from [12] show that 8-bit TABLE II COMPUTATION COMPLEXITY AND PARAMETER SIZE OF STATE-OF-THE-ART NETWORKS.”
BackgroundSelf-citationBravo-Rocca, G., Liu, P., Guitart, J., Dholakia, A., Ellison, D. D., Falkanger, J., & Hodak, M. (2022) · Expert Systems with Applications · doi:10.1016/j.eswa.2022.117232 · Cited by 8 · see citing works
Quantized Guided Pruning for Efficient Hardware Implementations of Deep Neural Networks
Hacene, G. B., Gripon, V., Arzel, M., Farrugia, N., & Bengio, Y. (2020) · IEEE International New Circuits and Systems Conference (NEWCAS) · doi:10.1109/newcas49341.2020.9159769 · Cited by 8 · see citing works
A Heterogeneous RISC-V Processor for Efficient DNN Application in Smart Sensing System
Zhang, H., Wu, X., Du, Y., et al. (2021) · Sensors · doi:10.3390/s21196491 · Cited by 6 · see citing works
“In addition, the utilization of the computing unit is limited by the high latency and low bandwidth of memory access [24], since the computing unit remain idle, waiting for data to be transferred from memory.”
BackgroundA Hardware/Software Co-design Method for Approximate Semi-Supervised K-Means Clustering
Huang, P., Wang, C., Ma, R., et al. (2018) · IEEE Computer Society Annual Symposium on VLSI · doi:10.1109/isvlsi.2018.00110 · Cited by 6 · see citing works
“The advantages of approximate computing cannot be fully exploited by only considering hardware or software; therefore, an hardware/software (HW/SW) co-design [5], [15], [16] must be considered to change the abstractions and relationships between hardware and software for a trade-off between accuracy and efficiency [15…”
BackgroundCodNN – Robust Neural Networks From Coded Classification
Raviv, N., Jain, S., Upadhyaya, P., et al. (2020) · IEEE International Symposium on Information Theory (ISIT) · doi:10.1109/isit44484.2020.9174480 · Cited by 6 · see citing works
“A massive amount of academic and industrial research is being devoted to implementing DNNs in hardware [4].”
BackgroundToolflow for the algorithm-hardware co-design of memristive ANN accelerators
Wabnitz, M., & Gemmeke, T. (2023) · Memories - Materials Devices Circuits and Systems · doi:10.1016/j.memori.2023.100066 · Cited by 5 · see citing works
DiaNet: An Efficient Multi-Grained Re-configurable Neural Network in Silicon
Zhang, R., Chen, Y., Nakada, T., & Nakashima, Y. (2019) · IEEE International System-on-Chip Conference (SOCC) · doi:10.1109/socc46988.2019.1570548015 · Cited by 5 · see citing works
EXPRESS: A Framework for Execution Time Prediction of Concurrent CNNs on Xilinx DPU Accelerator
Goel, S., Kedia, R., Sen, R., et al. (2024) · ACM Transactions on Embedded Computing Systems · doi:10.1145/3697835 · Cited by 4 · see citing works
“In this work, we consider Deep learning Processor Unit ( DPU ) [1], an FPGA-based CNN accelerator that originated from academia [18, 19, 35, 44] and is currently available as a commercial product by Xilinx.”
Hardware/Software Co-design for Convolutional Neural Networks Acceleration: A Survey and Open Issues
Pham‐Quoc, C., Nguyen, X.-Q., & Thinh, T. N. (2021) · Lecture notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering · doi:10.1007/978-3-030-93179-7_13 · Cited by 4 · see citing works
Tang, S.-N., Liao, J.-C., Chiu, C.-K., et al. (2021) · Electronics · doi:10.3390/electronics10202511 · Cited by 4 · see citing works
“(2D) convolution is often accelerated at the HW side, while other low-effort CNN operations, such as maximum pooling, fully-connected (FC) layer execution and system controls are processed at the SW end [39,40].”
BackgroundXie, X., Hu, X., Gu, P., Li, S., Ji, Y., & Xie, Y. (2020) · ACM Transactions on Architecture and Code Optimization · doi:10.1145/3417709 · Cited by 3 · see citing works
Self-citationHigh-efficient MPSoC-based CNNs accelerator with optimized storage and dataflow
Zhang, Y., Jiang, H., Liu, X., Cao, H., & Du, Y. (2021) · The Journal of Supercomputing · doi:10.1007/s11227-021-03909-y · Cited by 4 · see citing works
“Compared with the current typical accelerators [13, 14, 16, 41], the accelerator proposed can increase the average system throughput by 20.96 × and the maximum is 41x.”
BackgroundMethodInfluentialBelabed, T., Silva, V. R. G., Quenon, A., et al. (2021) · Sensors · doi:10.3390/s21186050 · Cited by 3 · see citing works
“In addition, by offering a Python interface while relying on low-level hardware design, it brings together hardware designs and software development skills, which helps to fasten and improve the design process [9,10].”
MethodTrusted Heterogeneous Disaggregated Architectures
Koshiba, A., Gust, F., Pritzi, J., Vahldiek-Oberwagner, A., Santos, N., & Bhatotia, P. (2023) · ACM SIGOPS Asia-Pacific Workshop on Systems (APSys) · doi:10.1145/3609510.3609812 · Cited by 4 · see citing works
Liu, B., Wu, Q., Zhang, Y., et al. (2020) · Security and Communication Networks · doi:10.1155/2020/5218612 · Cited by 3 · see citing works
Aizaz, Z., Khare, K., & Tirmizi, A. (2023) · Lecture notes in networks and systems · doi:10.1007/978-981-99-3963-3_43 · Cited by 2 · see citing works
Operator Optimization Oriented Person Re-Identification
Cao, Q., Wang, B., Dong, G., et al. (2022) · Journal of Physics Conference Series · doi:10.1088/1742-6596/2284/1/012019 · Cited by 2 · see citing works
“[ 21,22,23] achieve high frame rate on smaller devices, but still cannot make up for the loss of accuracy of their classification [24] on ImageNet.”
BackgroundSelf-citationCentralized Generic Interfaces in Hardware/Software Co-design for AI Accelerators
Chae, D., & Kapoor, P. (2020) · doi:10.1145/3387940.3392225 · Cited by 2 · see citing works
“The hardware/software co-design for neural network accelerators is mandatory because hardware and its applications are tightly coupled in deep learning [3].”
BackgroundZou, J., Qu, C., Zhou, Q., et al. (2025) · International Conference on Signal Processing Systems (ICSPS) · doi:10.1109/icsps66615.2025.11348023 · Cited by 1 · see citing works
“Guo et al. [7] proposed a co-optimization framework integrating pruning and quantization techniques.”
Marium, S. M., & Chen, S. (2026) · Microelectronics · doi:10.3390/microelectronics2020010 · Cited by 1 · see citing works
Cheng, Y., Wong, N., Liu, X., Ni, L., Chen, H., & Yu, H. (2019) · IEEE International Conference on ASIC (ASICON) · doi:10.1109/asicon47005.2019.8983497 · Cited by 1 · see citing works
“As most CNN filters are of small sizes (3×3 and 5×5), network pruning [4] may not be suitable.”
BackgroundMulti-dimensional Impact Detection and Diagnosis in Cellular Networks
Qureshi, M. A., Qiu, L., Mahimkar, A. A., et al. (2020) · International Conference on Mobility, Sensing and Networking (MSN) · doi:10.1109/msn50589.2020.00093 · Cited by 1 · see citing works
“For example, [44], [45] propose interesting algorithms to compress the neural network structure ( e.g. , learning only important connections, weights quantization, using Huffman coding).”
An FPGA Based Hardware Accelerator for Classification of Handwritten Digits
Ram, R., Chaturvedi, N. D., Saurav, S., et al. (2019) · Advances in intelligent systems and computing · doi:10.1007/978-3-030-16657-1_88 · Cited by 1 · see citing works
An FPGA-Based Solution for Convolution Operation Acceleration
Pham-Dinh, T., Bach, B. G., Luu-Trinh, L., et al. (2022) · Lecture notes on data engineering and communications technologies · doi:10.1007/978-3-031-15063-0_26 · Cited by 1 · see citing works
“Some of them try to improve parallelism by exploiting the huge amount of hardware resources in FPGA such as research in [3], [7], [8], [9].”
BackgroundA Versatile Acceleration Framework for Machine Learning Algorithms
Li, X., & Wang, Y. E. (2019) · IEEE International Conference on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom) · doi:10.1109/ispa-bdcloud-sustaincom-socialcom48970.2019.00076
“In [7], two FPGA-based accelerators were proposed to improve the performance of CNN and RNN and the author also proposed a Hardware-Software Co-design approach to address the rapid development of deep learning models.”
MethodSelf-citationCodNN -- Robust Neural Networks From Coded ClassificationPreprint
Raviv, N., Jain, S., Upadhyaya, P., et al. (2020) · arXiv (Cornell University) · doi:10.48550/arxiv.2004.10700
“A massive amount of academic and industrial research is being devoted to implementing DNNs in hardware [4].”
BackgroundEnergy-Efficient CNNs Accelerator Implementation on FPGA with Optimized Storage and Dataflow
Zhang, Y., Jiang, H., Li, X., et al. (2021) · IEEE International Conference on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom) · doi:10.1109/ispa-bdcloud-socialcom-sustaincom52081.2021.00166
“Compared with the current typical four accelerators [6, 7, 8, 16], the proposed accelerator has obvious advantages in throughput.”
BackgroundReprogrammable Optical Logic Circuit Using Opto-Electro-Mechanical Device
Deb, A. (2022) · Lecture notes in electrical engineering · doi:10.1007/978-981-16-9124-9_13
Hyperspherical Quantization: Toward Smaller and More Accurate Models
Liu, D., Chen, X., Ma, C., & Liu, X. (2023) · IEEE Winter Conference on Applications of Computer Vision · doi:10.1109/wacv56688.2023.00523
FPGA-Based Artificial Intelligence Accelerator for On-Board Processing of Aerial Scenes
AbdElkarim, O., Sherif, S., Inoue, K., Zewail, R., & Sayed, M. S. (2025) · doi:10.1109/icm66518.2025.11322530
- Authors
- Guo, K., Han, S., Yao, S., Wang, Y., Xie, Y., & Yang, H.
- Affiliations
- Tsinghua University (CN)
- Stanford University (US)
- University of California, Santa Barbara (US)
- Venue
- IEEE Micro
- Published
- 2017-03
- Volume
- 37
- Issue
- 2
- Pages
- 18-25
- ISSN
- 0272-1732 (ISSN-L)
- 1937-4143
- OpenAlex
- W2613574453
- Cited by
- 78
- References
- 0
- Citations by year
- 2026: 1 · 2025: 2 · 2024: 1 · 2023: 10 · 2022: 9 · 2021: 19 · 2020: 15 · 2019: 12 · 2018: 9
- FWCI
- 4.09
- Type
- journal article
- Language
- en
- Open access
- closed
- Licence
- Locations
- IEEE Micro (publishedVersion)
- Rare & Special e-Zone (The Hong Kong University of Science and Technology) (submittedVersion)
- Funders
- Princeton University
- Tsinghua University
- Topics
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
- Keywords
- hardware-software co-design, neural network acceleration, model compression, energy efficiency, convolutional neural networks, recurrent neural networks, compilation, energy consumption reduction
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
What counts as a claim ›How we measure confidence ›How we check this ›
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