The DOI matches its Crossref record; 6 of the 6 references it cites were found in a registry or an index.
Towards efficient deep neural network training by FPGA-based batch-level parallelism
Open accessAbstract
Abstract Training deep neural networks (DNNs) requires a significant amount of time and resources to obtain acceptable results, which severely limits its deployment in resource-limited platforms. This paper proposes DarkFPGA, a novel customizable framework to efficiently accelerate the entire DNN training on a single FPGA platform. First, we explore batch-level parallelism to enable efficient FPGA-based DNN training. Second, we devise a novel hardware architecture optimised by a batch-oriented data pattern and tiling techniques to effectively exploit parallelism. Moreover, an analytical model is developed to determine the optimal design parameters for the DarkFPGA accelerator with respect to a specific network specification and FPGA resource constraints. Our results show that the accelerator is able to perform about 10 times faster than CPU training and about a third of the energy consumption than GPU training using 8-bit integers for training VGG-like networks on the CIFAR dataset for the Maxeler MAX5 platform.
Overview
The claims and statistics of this paper haven’t been checked yet.
Run the check — free, no account needed. It reads the open-access text and checks the sources it cites.
Integrity signals
Registry
Cites
Statistics
Verification
Claims the paper makes
The claims and statistics of this paper haven’t been checked yet.
Run the check — free, no account needed. It reads the open-access text and checks the sources it cites.
Claims other papers make about this one
Each is checked against this paper’s own text: does it say what the citing paper says it does?
The cited source doesn’t support the claim as written.
In the citing paper
“In addition, batch-oriented data patterns, which refer to channel height width batch (CHWB) patterns, are implemented, using batch level parallelism but utilizing bandwidth as a compromise.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [32]
Checked by a reasoning model — may be wrong.
Experimental — accuracy not yet measuredThe cited source says what the claim attributes to it.
In the citing paper
“Batch-oriented data patterns and tiling techniques are used to optimize the hardware accelerator, which is able to effectively exploit parallelism.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [32]
The cited source says what the claim attributes to it.
In the citing paper
“Both forward and backward propagation on a homogenous FPGA system were able to improve the training by using a DarkFPGA accelerator with batch level parallelism.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [32]
The cited source says what the claim attributes to it.
In the citing paper
“Another proposed method, termed DarkFPGA by [32], uses batch-level parallelism hardware architecture.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [32]
Self-check
Percentages, sums and reported differences re-computed from the paper’s own numbers.
The self-check needs the paper’s full text.
Citations
Cites
Faster R-CNN: Towards Real-Time Object Detection with Region Proposal Networks
Ren, S., He, K., Girshick, R., & Sun, J. (2017) · IEEE Transactions on Pattern Analysis and Machine Intelligence · doi:10.1109/tpami.2016.2577031 · Cited by 73,472
Gradient-based learning applied to document recognition
Lecun, Y., Bottou, L., Bengio, Y., & Haffner, P. (1998) · Proceedings of the IEEE · doi:10.1109/5.726791 · Cited by 58,805
ImageNet Large Scale Visual Recognition Challenge
Russakovsky, O., Deng, J., Su, H., Krause, J., Satheesh, S., Ma, S., Huang, Z., Karpathy, A., Khosla, A., Bernstein, M., et al. (2015) · International Journal of Computer Vision · doi:10.1007/s11263-015-0816-y · Cited by 39,380
Mersenne twister: a 623-dimensionally equidistributed uniform pseudo-random number generator
Matsumoto, M., & Nishimura, T. (1998) · ACM Transactions on Modeling and Computer Simulation · doi:10.1145/272991.272995 · Cited by 5,780
Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
Zhang, C., Sun, G., Fang, Z., Zhou, P., Pan, P., & Cong, J. (2019) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2017.2785257 · Cited by 270
Maximum Performance Computing with Dataflow Engines
Pell, O., & Averbukh, V. (2012) · Computing in Science & Engineering · doi:10.1109/mcse.2012.78 · Cited by 99
Research works printed but not linked: 1
- Krishnan, 2017, Accelerator templates and runtime support for variable precision CNN, CISC Workshop
Cited by
Sorted by citations
Duan, Q., Huang, J., Hu, S., Deng, R., Lu, Z., & Yu, S. (2023) · IEEE Communications Surveys & Tutorials · doi:10.1109/comst.2023.3316615 · Cited by 189
Embedded Intelligence on FPGA: Survey, Applications and Challenges
Seng, K. P., Lee, P. J., & Ang, L. M. (2021) · Electronics · doi:10.3390/electronics10080895 · Cited by 105
“Another proposed method, termed DarkFPGA by [32], uses batch-level parallelism hardware architecture.”
MethodA Systematic Literature Review on Binary Neural Networks
Sayed, R., Azmi, H., Shawkey, H., Khalil, A. H., & Refky, M. A. (2023) · IEEE Access · doi:10.1109/access.2023.3258360 · Cited by 51
FPGA-based low-batch training accelerator for modern CNNs featuring high bandwidth memory
Venkataramanaiah, S. K., Suh, H.-S., Yin, S., Nurvitadhi, E., Dasu, A. R., Cao, Y. K., & Seo, J.-S. (2020) · doi:10.1145/3400302.3415643 · Cited by 33
Tang, Y., Zhang, X., Zhou, P., & Hu, J. (2022) · ACM Transactions on Design Automation of Electronic Systems · doi:10.1145/3505633 · Cited by 26
Metadata
- Authors
- Luo, C., Sit, M.-K., Fan, H., Liu, S., Luk, W., & Guo, C.
- Affiliations
- Fudan University (CN)
- Imperial College London (GB)
- Venue
- Journal of Semiconductors
- Publisher
- IOP Publishing
- Published
- 2020-02-01
- Volume
- 41
- Issue
- 2
- Pages
- 022403
- ISSN
- 1674-4926 (ISSN-L)
- 2058-6140
- OpenAlex
- W3004303566
- Cited by
- 26
- References
- 6
- Citations by year
- 2025: 2 · 2024: 4 · 2023: 7 · 2022: 8 · 2021: 3 · 2020: 2
- FWCI
- 4.20
- Type
- journal article
- Language
- en
- Open access
- bronze
- doi.org
- Licence
- Locations
- Journal of Semiconductors (publishedVersion)
- Topics
- Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Keywords
- FPGA, deep neural network training, hardware accelerators, tiling, energy efficiency, VGG, resource-constrained platforms
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
What counts as a claim ›How we measure confidence ›How we check this ›
Are you an author, or do you see a problem with this page? Request a review
How to cite
Cite CoChat for the checks on this page, and the paper for its own findings.
- This page
- CoChat. (2026). Citation check: Towards efficient deep neural network training by FPGA-based batch-level parallelism. https://app.cochat.ai/papers/10.1088/1674-4926/41/2/022403
- The paper
- Luo, C., Sit, M.-K., Fan, H., Liu, S., Luk, W., & Guo, C. (2020). Towards efficient deep neural network training by FPGA-based batch-level parallelism. Journal of Semiconductors. https://doi.org/10.1088/1674-4926/41/2/022403
