A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
Abstract
A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6 /spl mu/m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 11.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW.
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Bootstrapped switches provide low-distortion differential sampling by keeping the gate-to-source voltage of the effective switch transistor nearly constant.
“To provide a low distortion differential sampling, bootstrapped switches [9] were considered in the design.These switches keeps the gate to source voltage of an effective switch transistor nearly constant.”
From A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS (2021) · cites this paper as [9]
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Callegari, S., Rovatti, R., & Setti, G. (2005) · IEEE Transactions on Signal Processing · doi:10.1109/tsp.2004.839924 · Cited by 243 · see citing works
Stepanovic, D., & Nikolic, B. (2013) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2013.2239005 · Cited by 192 · see citing works
Al-Ashmouny, K. M., Chang, S.-I., & Yoon, E. (2012) · IEEE Transactions on Biomedical Circuits and Systems · doi:10.1109/tbcas.2012.2218105 · Cited by 28 · see citing works
A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS
Campos, A. L., Navarro, J., Luppe, M., & de Lima, E. R. (2021) · Analog Integrated Circuits and Signal Processing · doi:10.1007/s10470-020-01742-6 · Cited by 8 · see citing works
- Authors
- Abo, A. M., & Gray, P. R.
- Affiliations
- University of California, Berkeley (US)
- Venue
- IEEE Journal of Solid-State Circuits
- Published
- 1999-05
- Volume
- 34
- Issue
- 5
- Pages
- 599-606
- ISSN
- 0018-9200 (ISSN-L)
- OpenAlex
- W2099432139
- Cited by
- 923
- References
- 0
- Citations by year
- 2026: 11 · 2025: 15 · 2024: 20 · 2023: 24 · 2022: 21 · 2021: 29 · 2020: 14 · 2019: 17 · 2018: 31 · 2017: 32 · 2016: 29 · 2015: 36 · 2014: 45 · 2013: 34 · 2012: 52
- FWCI
- 21.77
- Type
- journal article
- Language
- ja
- Open access
- closed
- Locations
- IEEE Journal of Solid-State Circuits (publishedVersion)
- Topics
- Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Radio Frequency Integrated Circuit Design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Keywords
- pipelined ADC, low-voltage analog-to-digital conversion, CMOS, MOS switches, device reliability, 10-bit resolution, SNDR, integral nonlinearity, differential nonlinearity, low-power circuits
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