Cited by 28Analog and Mixed-Signal Circuit DesignNeuroscience and Neural EngineeringRadio Frequency Integrated Circuit Design

A 4 <formula formulatype="inline"><tex Notation="TeX">$\mu{\rm W}/{\rm Ch}$</tex></formula> Analog Front-End Module With Moderate Inversion and Power-Scalable Sampling Operation for 3-D Neural Microsystems

Al-Ashmouny, K. M., Sun-Il Chang, Euisik Yoon·2012·IEEE Transactions on Biomedical Circuits and Systems

Abstract

We report an analog front-end prototype designed in 0.25 μm CMOS process for hybrid integration into 3-D neural recording microsystems. For scaling towards massive parallel neural recording, the prototype has investigated some critical circuit challenges in power, area, interface, and modularity. We achieved extremely low power consumption of 4 μW/channel, optimized energy efficiency using moderate inversion in low-noise amplifiers (K of 5.98 × 10⁸ or NEF of 2.9), and minimized asynchronous interface (only 2 per 16 channels) for command and data capturing. We also implemented adaptable operations including programmable-gain amplification, power-scalable sampling (up to 50 kS/s/channel), wide configuration range (9-bit) for programmable gain and bandwidth, and 5-bit site selection capability (selecting 16 out of 128 sites). The implemented front-end module has achieved a reduction in noise-energy-area product by a factor of 5-25 times as compared to the state-of-the-art analog front-end approaches reported to date.

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Registry

Crossref · 10.1109/tbcas.2012.2218105

Cites

40 of 40 references verified0 citation errors · 0 not checkable

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  • Al-ashmouny et al. reported a 128-input channel neural recording IC in which only 16 inputs were selectively routed to the front-end amplifiers, achieving power and area reduction.

    “For example, Al-ashmouny et al. reported a 128-input channel neural recording IC [2] with only 16 inputs selectively routed to the front-end amplifiers, therefore achieving power and area reduction.”
  • Al-ashmouny et al. reported an implementation in which the ADC supply voltage was scalable according to sampling rate, throttling power consumption.

    “Similarly, Al-ashmouny et al. [2] reported an implementation where the supply voltage of the ADC was made scalable according to the sampling rate, throttling the power consumption.”

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Cited by

Authors
Al-Ashmouny, K. M., Chang, S.-I., & Yoon, E.
Affiliations
University of Michigan (US)
Venue
IEEE Transactions on Biomedical Circuits and Systems
Published
2012-10
Volume
6
Issue
5
Pages
403-413
ISSN
  • 1932-4545 (ISSN-L)
  • 1940-9990
OpenAlex
W1980234289
Cited by
28
References
40
Citations by year
2024: 1 · 2023: 1 · 2022: 1 · 2021: 1 · 2020: 1 · 2018: 1 · 2017: 5 · 2016: 5 · 2015: 3 · 2014: 3 · 2013: 4 · 2012: 2
FWCI
2.19
Type
journal article
Language
en
Open access
closed
Locations
  • IEEE Transactions on Biomedical Circuits and Systems (publishedVersion)
  • PubMed (publishedVersion)
Topics
  • Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
  • Life Sciences › Neuroscience › Cellular and Molecular Neuroscience › Neuroscience and Neural Engineering
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Radio Frequency Integrated Circuit Design
Keywords
analog front-end, neural recording, low-power circuits, moderate inversion, low noise amplifier, asynchronous interfaces, hybrid integration, CMOS
MeSH terms
Action Potentials, Amplifiers, Electronic, Biomedical Engineering, Brain, Humans, Microelectrodes, Models, Neurological, Monitoring, Physiologic, Semiconductors, Imaging, Three-Dimensional, Electrophysiological Phenomena

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