The DOI matches its Crossref record; 12 of the 12 references it cites were found in a registry or an index.
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Abstract
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.
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Cites
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Metadata
- Authors
- Roy, K., Mukhopadhyay, S., & Mahmoodi-Meimand, H.
- Venue
- Proceedings of the IEEE
- Published
- 2003-02
- Volume
- 91
- Issue
- 2
- Pages
- 305-327
- ISSN
- 0018-9219 (ISSN-L)
- OpenAlex
- W2131862714
- Cited by
- 2,368
- References
- 12
- FWCI
- 85.48
- Type
- journal article
- Language
- en
- Open access
- closed
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- Roy, K., Mukhopadhyay, S., & Mahmoodi-Meimand, H. (2003). Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proceedings of the IEEE. https://doi.org/10.1109/jproc.2002.808156
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