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A Flexible and Fast PyTorch Toolkit for Simulating Training and Inference on Analog Crossbar Arrays
Open accessAbstract
We introduce the IBM ANALOG HARDWARE ACCELERATION KIT, a new and first of a kind open source toolkit to simulate analog crossbar arrays in a convenient fashion from within PYTORCH (freely available at https://github.com/IBM/aihwkit). The toolkit is under active development and is centered around the concept of an “analog tile” which captures the computations performed on a crossbar array. Analog tiles are building blocks that can be used to extend existing network modules with analog components and compose arbitrary artificial neural networks (ANNs) using the flexibility of the PYTORCH framework. Analog tiles can be conveniently configured to emulate a plethora of different analog hardware characteristics and their non-idealities, such as device-to-device and cycle-to-cycle variations, resistive device response curves, and weight and output noise. Additionally, the toolkit makes it possible to design custom unit cell configurations and to use advanced analog optimization algorithms such as Tiki-Taka. Moreover, the backward and update behavior can be set to “ideal" to enable hardware-aware training features for chips that target inference acceleration only. To evaluate the inference accuracy of such chips over time, we provide statistical programming noise and drift models calibrated on phase-change memory hardware. Our new toolkit is fully GPU accelerated and can be used to conveniently estimate the impact of material properties and non-idealities of future analog technology on the accuracy for arbitrary ANNs.
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“However, the IBM toolkit [18] does not assess the hardware chip's runtime, latency, and power performance.”
From Framework for In-Memory Computing Based on Memristor and Memcapacitor for On-Chip Training (2023) · cites this paper as [18]
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“It has become increasingly apparent that accuracy on chips that are designed for inference benefit greatly from “hardwareaware” training, where the DNN workload is trained (or finetuned) in software with some analog noise and non-idealities in the forward pass, but with otherwise perfect backward and update pass [3],…”
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Metadata
- Authors
- Rasch, M. J., Moreda, D., Gokmen, T., Le Gallo, M., Carta, F., Goldberg, C., El Maghraoui, K., Sebastian, A., & Narayanan, V.
- Affiliations
- IBM (United States) (US)
- IBM Research
- Venue
- 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS)
- Publisher
- IEEE
- Published
- 2021-06-06
- Pages
- 1-4
- OpenAlex
- W3148526109
- Cited by
- 160
- References
- 16
- Citations by year
- 2026: 28 · 2025: 36 · 2024: 40 · 2023: 32 · 2022: 18 · 2021: 6
- FWCI
- 37.68
- Type
- conference paper
- Language
- en
- Open access
- green
- arxiv.org
- Locations
- IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) (publishedVersion)
- arXiv (Cornell University) (submittedVersion)
- arXiv (Cornell University) (cc-by)
- Funders
- Rensselaer Polytechnic Institute
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Ferroelectric and Negative Capacitance Devices
- Physical Sciences › Computer Science › Artificial Intelligence › Neural Networks and Reservoir Computing
- Keywords
- analog neural networks, hardware-aware training, phase-change memory, device-to-device variation, cycle-to-cycle variation, hardware acceleration, GPU-accelerated simulation, open-source software toolkit
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