Narayanan, Vijay
IBM (United States) · IBM Research - Thomas J. Watson Research Center
11 papers on CoChatORCID 0009-0008-8433-963X
Most cited papers
- Verified
A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference
Le Gallo, M., Khaddam-Aljameh, R., Stanisavljevic, M., Vasilopoulos, A., Kersting, B., Dazzi, M., Karunaratne, G., Brändli, M., Singh, A., Müller, S. M., et al. (2023) · Nature Electronics
Advanced Memory and Neural ComputingLow-power high-performance VLSI design
Cited by 310
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An analog-AI chip for energy-efficient speech recognition and transcription
Ambrogio, S., Narayanan, P., Okazaki, A., Fasoli, A., Mackin, C., Hosokawa, K., Nomura, A., Yasuda, T., Chen, A., Friz, A., et al. (2023) · Nature
Advanced Memory and Neural ComputingLow-power high-performance VLSI design
Cited by 269
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Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators
Rasch, M. J., Mackin, C., Le Gallo, M., Chen, A., Fasoli, A., Odermatt, F., Li, N., Nandakumar, S. R., Narayanan, P., Tsai, H., et al. (2023) · Nature Communications
Advanced Memory and Neural ComputingAdvanced Neural Network Applications
Cited by 213
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A Flexible and Fast PyTorch Toolkit for Simulating Training and Inference on Analog Crossbar Arrays
Rasch, M. J., Moreda, D., Gokmen, T., Le Gallo, M., Carta, F., Goldberg, C., El Maghraoui, K., Sebastian, A., & Narayanan, V. (2021) · 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS)
Advanced Memory and Neural ComputingFerroelectric and Negative Capacitance Devices
Cited by 160
- Verified
HERMES-Core—A 1.59-TOPS/mm 2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs
Khaddam-Aljameh, R., Stanisavljevic, M., Fornt Mas, J., Karunaratne, G., Brändli, M., Liu, F., Singh, A., Müller, S. M., Egger, U., Petropoulos, A., et al. (2022) · IEEE Journal of Solid-State Circuits
Advanced Memory and Neural ComputingLow-power high-performance VLSI design
Cited by 144
- Verified
HERMES Core – A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing
Khaddam-Aljameh, R., Stanisavljevic, M., Fornt Mas, J., Karunaratne, G., Braendli, M., Liu, F., Singh, A., Müller, S. M., Egger, U., Petropoulos, A., et al. (2021) · 2021 Symposium on VLSI Circuits
Advanced Memory and Neural ComputingLow-power high-performance VLSI design
Cited by 124
- Verified
Fully On-Chip MAC at 14 nm Enabled by Accurate Row-Wise Programming of PCM-Based Weights and Parallel Vector-Transport in Duration-Format
Narayanan, P., Ambrogio, S., Okazaki, A., Hosokawa, K., Tsai, H., Nomura, A., Yasuda, T., Mackin, C., Lewis, S. C., Friz, A., et al. (2021) · IEEE Transactions on Electron Devices
Advanced Memory and Neural ComputingLow-power high-performance VLSI design
Cited by 85
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A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh
Jain, S., Tsai, H., Chen, C.-T., Muralidhar, R., Boybat, I., Frank, M. M., Woźniak, S., Stanisavljevic, M., Adusumilli, P., Narayanan, P., et al. (2023) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Advanced Memory and Neural ComputingParallel Computing and Optimization Techniques
Cited by 76
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Mushroom-Type phase change memory with projection liner: An array-level demonstration of conductance drift and noise mitigation
Bruce, R. L., Sarwat, S. G., Boybat, I., Cheng, C.-W., Kim, W., Nandakumar, S. R., Mackin, C., Philip, T., Liu, Z., Brew, K., et al. (2021) · 2021 IEEE International Reliability Physics Symposium (IRPS)
Advanced Memory and Neural ComputingPhase-change materials and chalcogenides
Cited by 23
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Gradient descent-based programming of analog in-memory computing cores
Büchel, J., Vasilopoulos, A., Kersting, B., Odermatt, F., Brew, K., Ok, I., Choi, S., Saraf, I., Chan, V., Philip, T., et al. (2022) · 2022 International Electron Devices Meeting (IEDM)
Advanced Memory and Neural ComputingFerroelectric and Negative Capacitance Devices
Cited by 18
- Verified
Gradient descent-based programming of analog in-memory computing cores
Büchel, J., Sebastian, A., Kersting, B., Odermatt, F., Brew, K., Ok, I., Choi, S., Vasilopoulos, A., Chan, V., Philip, T., et al. (2023) · Proceedings of the Neuromorphic Materials, Devices, Circuits and Systems
Advanced Memory and Neural ComputingFerroelectric and Negative Capacitance Devices
Cited by 1
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