The DOI matches its Crossref record; 12 of the 12 references it cites were found in a registry or an index.
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
Abstract
Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of analog neuron circuits; (b) the enormous area overhead of learning circuits, which grows with the number of synapses; and (c) the need to implement all inter-neuron communication via off-chip address-events. In this work, a new architecture is proposed to overcome these challenges by combining innovations in computation, memory, and communication, respectively, to leverage (a) robust digital neuron circuits; (b) novel transposable SRAM arrays that share learning circuits, which grow only with the number of neurons; and (c) crossbar fan-out for efficient on-chip inter-neuron communication. Through tight integration of memory (synapses) and computation (neurons), a highly configurable chip comprising 256 neurons and 64K binary synapses with on-chip learning based on spike-timing dependent plasticity is demonstrated in 45nm SOI-CMOS. Near-threshold, event-driven operation at 0.53V is demonstrated to maximize power efficiency for real-time pattern classification, recognition, and associative memory tasks. Future scalable systems built from the foundation provided by this work will open up possibilities for ubiquitous ultra-dense, ultra-low power brain-like cognitive computers.
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Citations
Cites
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Self-citationPractical Strategies for Power-Efficient Computing Technologies
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Self-citationLearning in Silicon: Timing is Everything
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Synaptic electronics: materials, devices and applications
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Self-citationNeuromorphic computing using non-volatile memory
Burr, G. W., Shelby, R. M., Sebastian, A., Kim, S., Kim, S., Sidler, S., Virwani, K., Ishii, M., Narayanan, P., Fumarola, A., et al. (2017) · Advances in Physics: X · doi:10.1080/23746149.2016.1259585 · Cited by 1,107
Neuro-inspired computing chips
Zhang, W., Gao, B., Tang, J., Yao, P., Yu, S., Chang, M.-F., Yoo, H.-J., Qian, H., & Wu, H. (2020) · Nature Electronics · doi:10.1038/s41928-020-0435-7 · Cited by 892
Chi, P., Li, S., Xu, C., Zhang, T., Zhao, J., Liu, Y., Wang, Y., & Xie, Y. (2016) · 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA) · doi:10.1109/isca.2016.13 · Cited by 573
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Metadata
- Authors
- Seo, J.-S., Brezzo, B., Liu, Y., Parker, B. D., Esser, S. K., Montoye, R. K., Rajendran, B., Tierno, J. A., Chang, L., Modha, D. S., & Friedman, D. J.
- Venue
- 2011 IEEE Custom Integrated Circuits Conference (CICC)
- Publisher
- IEEE
- Published
- 2011-09
- Pages
- 1-4
- OpenAlex
- W2131763976
- Cited by
- 344
- References
- 12
- FWCI
- 27.84
- Type
- conference paper
- Language
- en
- Open access
- closed
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- Seo, J.-S., Brezzo, B., Liu, Y., Parker, B. D., Esser, S. K., Montoye, R. K., Rajendran, B., Tierno, J. A., Chang, L., Modha, D. S., & Friedman, D. J. (2011). A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. 2011 IEEE Custom Integrated Circuits Conference (CICC). https://doi.org/10.1109/cicc.2011.6055293
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