The DOI matches its Crossref record; 7 of the 7 references it cites were found in a registry or an index.
Characterizing the effects of transient faults on a high-performance processor pipeline
Abstract
The progression of implementation technologies into the sub-100 nanometer lithographies renew the importance of understanding and protecting against single-event upsets in digital systems. In this work, the effects of transient faults on high performance microprocessors is explored. To perform a thorough exploration, a highly detailed register transfer level model of a deeply pipelined, out-of-order microprocessor was created. Using fault injection, we determined that fewer than 15% of single bit corruptions in processor state result in software visible errors. These failures were analyzed to identify the most vulnerable portions of the processor, which were then protected using simple low-overhead techniques. This resulted in a 75% reduction in failures. Building upon the failure modes seen in the microarchitecture, fault injections into software were performed to investigate the level of masking that the software layer provides. Together, the baseline microarchitectural substrate and software mask more than 9 out of 10 transient faults from affecting correct program execution.
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Cites
Modeling the effect of technology trends on the soft error rate of combinational logic
Shivakumar, P., Kistler, M., Keckler, S. W., Burger, D., & Alvisi, L. (2003) · Proceedings International Conference on Dependable Systems and Networks · doi:10.1109/dsn.2002.1028924 · Cited by 1,449
Mukherjee, S. S., Weaver, C. T., Emer, J., Reinhardt, S. K., & Austin, T. M. (2003) · Cited by 840
Mukherjee, S. S., Weaver, C., Emer, J., Reinhardt, S. K., & Austin, T. (2004) · 22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449) · doi:10.1109/micro.2003.1253181 · Cited by 656
The microarchitecture of the Pentium 4 processor
Hinton, G. (2001) · Medical Entomology and Zoology · Cited by 587
Comparison of error rates in combinational and sequential logic
Buchner, S., Baze, M., Brown, D., McMorrow, D., & Melinger, J. (1997) · IEEE Transactions on Nuclear Science · doi:10.1109/23.659037 · Cited by 244
A gate-level simulation environment for alpha-particle-induced transient faults
Cha, H., Rudnick, E. M., Patel, J. H., Iyer, R. K., & Choi, G. S. (1996) · IEEE Transactions on Computers · doi:10.1109/12.544481 · Cited by 139
Effects of transient gate-level faults on program behavior
Czeck, E. W., & Siewiorek, D. P. (2002) · IEEE International Symposium on Fault-Tolerant Computing · doi:10.1109/ftcs.1990.89371 · Cited by 103
Cited by
Architecture Design for Soft Errors
(2008) · Elsevier eBooks · doi:10.1016/b978-0-12-369529-1.x5001-0 · Cited by 365
FIdelity: Efficient Resilience Analysis Framework for Deep Learning Accelerators
He, Y., Balaprakash, P., & Li, Y. (2020) · 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) · doi:10.1109/micro50266.2020.00033 · Cited by 83
Metadata
- Authors
- Wang, N. J., Quek, J., Rafacz, T. M., & Patel, S. J.
- Venue
- International Conference on Dependable Systems and Networks, 2004
- Publisher
- IEEE
- Published
- 2004
- Pages
- 61-70
- OpenAlex
- W1976431848
- Cited by
- 397
- References
- 7
- FWCI
- 33.54
- Type
- conference paper
- Language
- en
- Open access
- closed
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