The DOI matches its Crossref record; 5 of the 5 references it cites were found in a registry or an index.
A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor
Abstract
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transients faults exist, but come at a cost. Designers clearly require accurate estimates of processor error rates to make appropriate cost/reliability tradeoffs. This paper describes a method for generating these estimates. A key aspect of this analysis is that some single-bit faults (such as those occurring in the branch predictor) do not produce an error in a program's output. We define a structure's architectural vulnerability factor (AVF) as the probability that a fault in that particular structure do not result in an error. A structure's error rate is the product of its raw error rate, as determined by process and circuit technology, and the AVF. Unfortunately, computing AVFs of complex structures, such as the instruction queue, can be quite involved. We identify numerous cases, such as prefetches, dynamically dead code, and wrong-path instructions, in which a fault do not affect, correct execution. We instrument a detailed 1A64 processor simulator to map bit-level microarchitectural state to these cases, generating per-structure AVF estimates. This analysis shows AVFs of 28% and 9% for the instruction queue and execution units, respectively, averaged across dynamic sections of the entire CPU2000 benchmark suite.
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Cites
Automatically characterizing large scale program behavior
Sherwood, T., Perelman, E., Hamerly, G., & Calder, B. (2002) · Proceedings of the 10th international conference on Architectural support for programming languages and operating systems · doi:10.1145/605397.605403 · Cited by 1,674
Modeling the effect of technology trends on the soft error rate of combinational logic
Shivakumar, P., Kistler, M., Keckler, S. W., Burger, D., & Alvisi, L. (2003) · Proceedings International Conference on Dependable Systems and Networks · doi:10.1109/dsn.2002.1028924 · Cited by 1,449
Single event upset at ground level
Normand, E. (1996) · IEEE Transactions on Nuclear Science · doi:10.1109/23.556861 · Cited by 620
DIVA: a reliable substrate for deep submicron microarchitecture design
Austin, T. M. (2003) · MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture · doi:10.1109/micro.1999.809458 · Cited by 380
Self-citationAsim: a performance model framework
Emer, J., Ahuja, P., Borch, E., Klauser, A., Luk, C.-K., Manne, S., Mukherjee, S. S., Patil, H., Wallace, S., Binkert, N., et al. (2002) · Computer · doi:10.1109/2.982918 · Cited by 223
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Cited by
Characterizing the effects of transient faults on a high-performance processor pipeline
Wang, N. J., Quek, J., Rafacz, T. M., & Patel, S. J. (2004) · International Conference on Dependable Systems and Networks, 2004 · doi:10.1109/dsn.2004.1311877 · Cited by 397
Analyzing and Increasing the Reliability of Convolutional Neural Networks on GPUs
Santos, F. F. D., Pimenta, P. F., Lunardi, C., Draghetti, L., Carro, L., Kaeli, D., & Rech, P. (2019) · IEEE Transactions on Reliability · doi:10.1109/tr.2018.2878387 · Cited by 226
SASSIFI: An architecture-level fault injection tool for GPU application resilience evaluation
Hari, S. K. S., Tsai, T., Stephenson, M., Keckler, S. W., & Emer, J. (2017) · 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) · doi:10.1109/ispass.2017.7975296 · Cited by 181
Self-citationNVBitFI: Dynamic Fault Injection for GPUs
Tsai, T., Hari, S. K. S., Sullivan, M., Villa, O., & Keckler, S. W. (2021) · 2021 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN) · doi:10.1109/dsn48987.2021.00041 · Cited by 93
Rech, P. (2024) · IEEE Transactions on Nuclear Science · doi:10.1109/tns.2024.3349956 · Cited by 75
Metadata
- Authors
- Mukherjee, S. S., Weaver, C., Emer, J., Reinhardt, S. K., & Austin, T.
- Venue
- 22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449)
- Publisher
- IEEE Comput. Soc
- Published
- 2003-01-01
- Pages
- 29-40
- ISSN
- 1072-4451 (ISSN-L)
- OpenAlex
- W4249144718
- Cited by
- 656
- References
- 5
- FWCI
- 25.56
- Type
- conference paper
- Language
- en
- Open access
- closed
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- Mukherjee, S. S., Weaver, C., Emer, J., Reinhardt, S. K., & Austin, T. (2004). A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor. 22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449). https://doi.org/10.1109/micro.2003.1253181
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Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
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