SgxPectre: Stealing Intel Secrets from SGX Enclaves Via Speculative Execution
Open accessAbstract
Speculative execution side-channel vulnerabilities in micro-architecture processors have raised concerns about the security of Intel SGX. To understand clearly the security impact of this vulnerability against SGX, this paper makes the following studies: First, to demonstrate the feasibility of the attacks, we present SgxPectre Attacks (the SGX-variants of Spectre attacks) that exploit speculative execution side-channel vulnerabilities to subvert the confidentiality of SGX enclaves. We show that when the branch prediction of the enclave code can be influenced by programs outside the enclave, the control flow of the enclave program can be temporarily altered to execute instructions that lead to observable cache-state changes. An adversary observing such changes can learn secrets inside the enclave memory or its internal registers, thus completely defeating the confidentiality guarantee offered by SGX. Second, to determine whether real-world enclave programs are impacted by the attacks, we develop techniques to automate the search of vulnerable code patterns in enclave binaries using symbolic execution. Our study suggests that nearly any enclave program could be vulnerable to SgxPectre Attacks since vulnerable code patterns are available in most SGX runtimes (e.g., Intel SGX SDK, Rust-SGX, and Graphene-SGX). Third, we apply SgxPectre Attacks to steal seal keys and attestation keys from Intel signed quoting enclaves. The seal key can be used to decrypt sealed storage outside the enclaves and forge valid sealed data; the attestation key can be used to forge attestation signatures. For these reasons, SgxPectre Attacks practically defeat SGX's security protection. Finally, we evaluate Intel's existing countermeasures against SgxPectre Attacks and discusses the security implications.
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An attestation server could be launched by the processor manufacturer, as with Intel's SGX attestation service, which is distinct from the cloud service provider.
“An attestation server could be launched by the processor manufacturer, as with Intel's SGX attestation service [27], which is distinct from the cloud service provider.”
From Confidential Computing Across Edge‐To‐Cloud for Machine Learning: A Survey Study (2025) · cites this paper as [27]
The ‘Defense via Centralized Attestation Services’ section says Intel’s attestation service arbitrates attestation requests from the ISV, supporting the Intel SGX example. Our copy does not establish the claimed distinction between that service and a cloud service provider. (LLM, conf=0.82)
Experimental — accuracy not yet measuredIntel SGX employs a memory encryption engine to provide assured secrecy, integrity, and freshness of CPU-DRAM traffic within enclave memory ranges.
“Intel Software Guard Extensions (SGX) [27] employs a memory encryption engine to provide assured secrecy, integrity, and freshness of the CPU-DRAM traffic within the enclave memory ranges.”
From Confidential Computing Across Edge‐To‐Cloud for Machine Learning: A Survey Study (2025) · cites this paper as [27]
Section B, “Intel SGX” (page not available), identifies memory encryption as an SGX primitive and says enclave memory is protected for confidentiality and integrity. Our copy does not establish the more specific claim that a memory encryption engine assures freshness of CPU–DRAM traffic. (LLM, conf=0.84)
Experimental — accuracy not yet measuredIntel SGX provides a remote attestation policy that evaluates the enclave identity, the integrity of the code inside it, and guarantees the authenticity of the Intel processor.
“Intel SGX provides remote attestation policy that evaluates the enclave identity, integrity of the code inside of it, and guarantees the authenticity of the Intel processor.”
From Confidential Computing Across Edge‐To‐Cloud for Machine Learning: A Survey Study (2025) · cites this paper as [27]
The Remote Attestation section (page not provided) says attestation is used to prove that a claimed enclave runs on an SGX-enabled processor, supporting the enclave and processor-verification aspects. It does not explicitly say that attestation evaluates the integrity of the code inside the enclave. The Extracting attestation key section also demonstrates that a stolen key can produce a valid quote without running the enclave on SGX, so processor authenticity is not guaranteed without qualification. (LLM, conf=0.86)
Experimental — accuracy not yet measuredIntel SGX proposes dynamic memory isolation to limit potential damage from side-channel attacks by isolating memory regions during execution phases.
“Intel SGX proposes dynamic memory isolation to limit the potential damage from side-channel attacks by isolating memory regions during the execution phases.”
From Confidential Computing Across Edge‐To‐Cloud for Machine Learning: A Survey Study (2025) · cites this paper as [27]
The Intel SGX section describes enclave memory isolation during execution, and the Introduction says it protects code and data from other software. Neither section describes the isolation as dynamic or says it is proposed to limit damage from side-channel attacks; the paper’s “Leaking Secrets via Side Channels” section instead describes how such attacks can leak enclave information. Page numbers are unavailable in our copy. (LLM, conf=0.86)
Experimental — accuracy not yet measuredDynamic memory isolation reduces exposure to timing-based attacks and improves the security of confidential processing.
“This approach reduces exposure to timing-based attacks and improves the security of the confidential processing [27].”
From Confidential Computing Across Edge‐To‐Cloud for Machine Learning: A Survey Study (2025) · cites this paper as [27]
The paper’s “Leaking Secrets via Side Channels” section (page unavailable) says enclave memory is not shared with the outside world, preventing ordinary FLUSH+RELOAD attacks. But it also explains how SGXPECTRE can use that timing-based channel despite the separation. The copy does not establish that dynamic memory isolation, as an approach, improves the security of confidential processing. (LLM, conf=0.78)
Experimental — accuracy not yet measured
TEEs are inherently hardware-dependent and may be vulnerable to microarchitectural attacks.
“TEE are inherently hardware-dependent and may be vulnerable to microarchitectural attacks [38], [39], [40], [41], [42], [43].”
From Hollow-LLM Attack: Computationally Trivial Weights in Zero-Knowledge Verification of LLM Inference (2026) · cites this paper as [42]
The Intel SGX section describes SGX as a processor architecture extension whose enclaves are created and maintained by the processor. The paper also reports microarchitectural attacks that can expose secrets in SGX enclaves. It supports SGX as an example, but does not establish that TEEs generally are inherently hardware-dependent. (LLM, conf=0.82)
Experimental — accuracy not yet measuredRemote attestation serves as a verification protocol for the service provider to evaluate the health of enclave(s) created at a remote location.
“Remote attestation serves as a verification protocol for the service provider to evaluate the health of enclave(s) created at a remote location [27,53,54].”
From Confidential Computing Across Edge‐To‐Cloud for Machine Learning: A Survey Study (2025) · cites this paper as [27]
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Cites
Symbolic execution and program testing
King, J. C. (1976) · Communications of the ACM · doi:10.1145/360248.360252 · Cited by 3,001 · see citing works
Spectre Attacks: Exploiting Speculative Execution
Kocher, P. C., Horn, J., Fogh, A., Genkin, D., Gruss, D., Haas, W., Hamburg, M., Lipp, M., Mangard, S., Prescher, T., et al. (2019) · IEEE Symposium on Security and Privacy (S&P) · doi:10.1109/sp.2019.00002 · Cited by 1,847 · see citing works
Cache Attacks and Countermeasures: The Case of AES
Osvik, D. A., Shamir, A., & Tromer, E. (2005) · Lecture notes in computer science · doi:10.1007/11605805_1 · Cited by 1,362 · see citing works
The geometry of innocent flesh on the bone
Shacham, H. (2007) · Proceedings of the ACM Conference on Computer and Communications Security · doi:10.1145/1315245.1315313 · Cited by 1,294 · see citing works
Innovative instructions and software model for isolated execution
Mckeen, F., Alexandrovich, I., Berenzon, A., Rozas, C. V., Shafi, H., Shanbhogue, V., & Savagaonkar, U. R. (2013) · Hardware and Architectural Support for Security and Privacy · doi:10.1145/2487726.2488368 · Cited by 1,103 · see citing works
Concentrated Differential Privacy: Simplifications, Extensions, and Lower Bounds
Bun, M., & Steinke, T. (2016) · Theory of Cryptography Conference · doi:10.1007/978-3-662-53641-4_24 · Cited by 1,045 · see citing works
Last-Level Cache Side-Channel Attacks are Practical
Liu, F., Yarom, Y., Ge, Q., Heiser, G. A., & Lee, R. B.-L. (2015) · IEEE Symposium on Security and Privacy (S&P) · doi:10.1109/sp.2015.43 · Cited by 1,036 · see citing works
FLUSH+RELOAD: a high resolution, low noise, L3 cache side-channel attack
Yarom, Y., & Falkner, K. E. K. (2013) · Cited by 977 · see citing works
SOK: (State of) The Art of War: Offensive Techniques in Binary Analysis
Shoshitaishvili, Y., Wang, R., Salls, C., et al. (2016) · Proceedings - IEEE Symposium on Security and Privacy/Proceedings of the ... IEEE Symposium on Security and Privacy · doi:10.1109/sp.2016.17 · Cited by 964 · see citing works
Meltdown: reading kernel memory from user space
Lipp, M., Schwarz, M., Gruss, D., Prescher, T., Haas, W., Fogh, A., Horn, J., Mangard, S., Kocher, P. C., Genkin, D., et al. (2018) · USENIX Security Symposium · Cited by 821 · see citing works
Cross-VM side channels and their use to extract private keys
Zhang, Y., Juels, A., Reiter, M. K., & Ristenpart, T. (2012) · ACM SIGSAC Conference on Computer and Communications Security (CCS) · doi:10.1145/2382196.2382230 · Cited by 791 · see citing works
Self-citationControlled-Channel Attacks: Deterministic Side Channels for Untrusted Operating Systems
Xu, Y., Cui, W., & Peinado, M. (2015) · IEEE Symposium on Security and Privacy (S&P) · doi:10.1109/sp.2015.45 · Cited by 725 · see citing works
Foreshadow: Extracting the keys to the Intel SGX kingdom with transient out-of-order execution
Bulck, J. V., Minkin, M., Weisse, O., Genkin, D., Kasikci, B., Piessens, F., Silberstein, M., Wenisch, T. F., Yarom, Y., & Strackx, R. (2018) · Lirias (KU Leuven) · Cited by 667 · see citing works
VC3: Trustworthy Data Analytics in the Cloud Using SGX
Schuster, F., Costa, M., Cédric Fournet, A., Gkantsidis, C., Peinado, M., Mainar-Ruiz, G., & Russinovich, M. (2015) · IEEE Symposium on Security and Privacy (S&P) · doi:10.1109/sp.2015.10 · Cited by 594 · see citing works
Zhang, F., Cecchetti, E., Croman, K., Juels, A., & Shi, E. (2016) · ACM SIGSAC Conference on Computer and Communications Security (CCS) · doi:10.1145/2976749.2978326 · Cited by 583 · see citing works
SCONE: secure Linux containers with Intel SGX
(2016) · Operating Systems Design and Implementation · doi:10.5555/3026877.3026930 · Cited by 582 · see citing works
Cache Games -- Bringing Access-Based Cache Attacks on AES to Practice
Gullasch, D., Bangerter, E., & Krenn, S. (2011) · IEEE Symposium on Security and Privacy (S&P) · doi:10.1109/sp.2011.22 · Cited by 530 · see citing works
Shielding Applications from an Untrusted Cloud with Haven
Baumann, A., Peinado, M., & Hunt, G. C. (2015) · ACM Transactions on Computer Systems · doi:10.1145/2799647 · Cited by 509 · see citing works
New cache designs for thwarting software cache-based side channel attacks
Wang, Z., & Lee, R. B.-L. (2007) · Proceedings - International Symposium on Computer Architecture/Proceedings · doi:10.1145/1250662.1250723 · Cited by 505 · see citing works
Efficient Cache Attacks on AES, and Countermeasures
Tromer, E., Osvik, D. A., & Adi Shamir, Z. (2009) · Journal of Cryptology · doi:10.1007/s00145-009-9049-y · Cited by 443 · see citing works
Oblivious multi-party machine learning on trusted processors
Ohrimenko, O., Schuster, F., Cédric Fournet, A., Mehta, A., Nowozin, S., Vaswani, K., & Costa, M. (2016) · MPG.PuRe (Max Planck Society) · Cited by 402 · see citing works
Sanctum: Minimal Hardware Extensions for Strong Software Isolation
Costan, V. V., Lebedev, I. A., & Devadas, S. (2016) · Cited by 379 · see citing works
CATalyst: Defeating last-level cache side channel attacks in cloud computing
Liu, F., Ge, Q., Yarom, Y., et al. (2016) · Proceedings - International Symposium on High-Performance Computer Architecture/Proceedings · doi:10.1109/hpca.2016.7446082 · Cited by 374 · see citing works
Graphene-SGX: a practical library OS for unmodified applications on SGX
Tsai, C.-C., Porter, D. E., & Vij, M. (2017) · Cited by 372 · see citing works
Götzfried, J., Eckert, M., Schinzel, S., & Müller, T. (2017) · European Workshop on System Security · doi:10.1145/3065913.3065915 · Cited by 351 · see citing works
Malware Guard Extension: Using SGX to Conceal Cache Attacks
Schwarz, M., Weiser, S., Gruss, D., Maurice, C., & Mangard, S. (2017) · Lecture notes in computer science · doi:10.1007/978-3-319-60876-1_1 · Cited by 350 · see citing works
Using innovative instructions to create trustworthy software solutions
Hoekstra, M., Lal, R., Pappachan, P. M., Phegade, V., & del Cuvillo, J. (2013) · Hardware and Architectural Support for Security and Privacy · doi:10.1145/2487726.2488370 · Cited by 349 · see citing works
Irazoqui, G., Eisenbarth, T., & Sunar, B. (2015) · IEEE Symposium on Security and Privacy (S&P) · doi:10.1109/sp.2015.42 · Cited by 338 · see citing works
T-SGX: Eradicating Controlled-Channel Attacks Against Enclave Programs
Shih, M.-W., Lee, S., Kim, T., & Peinado, M. (2017) · Network and Distributed System Security Symposium · doi:10.14722/ndss.2017.23193 · Cited by 338 · see citing works
Inferring Fine-grained Control Flow Inside SGX Enclaves with Branch ShadowingPreprint
Lee, S., Shih, M.-W., Gera, P., Kim, T., Kim, H., & Peinado, M. (2016) · arXiv (Cornell University) · doi:10.48550/arxiv.1611.06952 · Cited by 337 · see citing works
Cross-Tenant Side-Channel Attacks in PaaS Clouds
Zhang, Y., Juels, A., Reiter, M. K., et al. (2014) · ACM SIGSAC Conference on Computer and Communications Security (CCS) · doi:10.1145/2660267.2660356 · Cited by 332 · see citing works
Self-citationLeaky Cauldron on the Dark Land: Understanding Memory Side-Channel Hazards in SGX
Wang, W., Chen, G., Pan, X., Zhang, Y., Wang, X., Bindschaedler, V., Tang, H., & Gunter, C. A. (2017) · Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security · doi:10.1145/3133956.3134038 · Cited by 320 · see citing works
Self-citationSTEALTHMEM: system-level protection against cache-based side channel attacks in the cloud
Kim, T., Peinado, M., & Mainar-Ruiz, G. (2012) · Cited by 309 · see citing works
Software Grand Exposure: SGX Cache Attacks Are PracticalPreprint
Brasser, F., Müller, U., Dmitrienko, A., Kostiainen, K., Čapkun, S., & Sadeghi, A. (2017) · arXiv (Cornell University) · doi:10.48550/arxiv.1702.07521 · Cited by 294 · see citing works
Covert and Side Channels Due to Processor Architecture
Wang, Z., & Lee, R. C. (2006) · Annual Computer Security Applications Conference · doi:10.1109/acsac.2006.20 · Cited by 270 · see citing works
Wait a Minute! A fast, Cross-VM Attack on AES
Irazoqui, G., İnci, M. S., Eisenbarth, T., & Sunar, B. (2014) · Lecture notes in computer science · doi:10.1007/978-3-319-11379-1_15 · Cited by 267 · see citing works
Opaque: an oblivious and encrypted distributed analytics platform
Zheng, W., Dave, A., Beekman, J. G., Popa, R. A., Gonzalez, J. E., & Stoica, I. G. (2017) · Networked Systems Design and Implementation · Cited by 248 · see citing works
Yet another MicroArchitectural Attack: exploiting I-Cache
Aciiçmez, O. (2007) · Proceedings of the 2007 ACM workshop on Computer security architecture · doi:10.1145/1314466.1314469 · Cited by 232 · see citing works
Maisuradze, G., & Rossow, C. (2018) · ACM SIGSAC Conference on Computer and Communications Security (CCS) · doi:10.1145/3243734.3243761 · Cited by 231 · see citing works
The AMD opteron processor for multiprocessor servers
Keltcher, C. N., McGrath, K., Ahmed, A., et al. (2003) · IEEE Micro · doi:10.1109/mm.2003.1196116 · Cited by 227 · see citing works
Random Fill Cache Architecture
Liu, F., & Lee, R. B. (2014) · Proceedings of the ... annual International Symposium on Microarchitecture/Proceedings of the annual International Symposium on Microarchitecture · doi:10.1109/micro.2014.28 · Cited by 216 · see citing works
Practical Mitigations for Timing-Based Side-Channel Attacks on Modern x86 Processors
Coppens, B., Verbauwhede, I. M. R., Bosschere, K. D., & Sutter, B. D. (2009) · IEEE Symposium on Security and Privacy (S&P) · doi:10.1109/sp.2009.19 · Cited by 215 · see citing works
Panoply: Low-TCB Linux Applications with SGX Enclaves
Shinde, S., Tien, D. L., Tople, S., & Saxena, P. (2017) · Network and Distributed System Security Symposium · doi:10.14722/ndss.2017.23500 · Cited by 201 · see citing works
NetSpectre: Read Arbitrary Memory over Network
Schwarz, M., Schwarzl, M., Lipp, M., et al. (2019) · Lecture notes in computer science · doi:10.1007/978-3-030-29959-0_14 · Cited by 200 · see citing works
Molnár, D., Piotrowski, M., Schultz, D., & Wagner, D. (2006) · Lecture notes in computer science · doi:10.1007/11734727_14 · Cited by 198 · see citing works
Spectre Returns! Speculation Attacks Using the Return Stack Buffer
Koruyeh, E. M., Khasawneh, K. N., Song, C., & Abu‐Ghazaleh, N. (2024) · IEEE Design and Test · doi:10.1109/mdat.2024.3352537 · Cited by 197 · see citing works
Preventing Page Faults from Telling Your Secrets
Shinde, S., Chua, Z. L., Narayanan, V., et al. (2016) · ACM Asia Conference on Computer and Communications Security (ASIA CCS) · doi:10.1145/2897845.2897885 · Cited by 196 · see citing works
Domnitser, L., Jaleel, A., Loew, J., Abu‐Ghazaleh, N., & Ponomarev, D. (2012) · ACM Transactions on Architecture and Code Optimization · doi:10.1145/2086696.2086714 · Cited by 192 · see citing works
Telling your secrets without page faults: stealthy page table-based attacks on enclaved execution
Bulck, J. V., Weichbrodt, N., Kapitza, R., et al. (2017) · Lirias · Cited by 183 · see citing works
Raccoon: closing digital side-channels through obfuscated execution
Rane, A., Lin, C., & Tiwari, M. (2015) · Cited by 182 · see citing works
Advances on Access-Driven Cache Attacks on AES
Neve, M., & Seifert, J. (2007) · Lecture notes in computer science · doi:10.1007/978-3-540-74462-7_11 · Cited by 180 · see citing works
Bulck, J. V., Piessens, F., & Strackx, R. (2017) · doi:10.1145/3152701.3152706 · Cited by 180 · see citing works
Ryoan: a distributed sandbox for untrusted computation on secret data
Hunt, T., Zhu, Z., Xu, Y., Peter, S., & Witchel, E. (2016) · Operating Systems Design and Implementation · doi:10.5555/3026877.3026919 · Cited by 174 · see citing works
Detecting Privileged Side-Channel Attacks in Shielded Execution with Déjà Vu
Chen, S., Zhang, X., Reiter, M. K., & Zhang, Y. (2017) · ACM Asia Conference on Computer and Communications Security (ASIA CCS) · doi:10.1145/3052973.3053007 · Cited by 172 · see citing works
Self-citationSGX-Shield: Enabling Address Space Layout Randomization for SGX Programs
Seo, J., Lee, B., Kim, S.-M., Shih, M.-W., Shin, I., Han, D., & Kim, T. (2017) · Network and Distributed System Security Symposium · doi:10.14722/ndss.2017.23037 · Cited by 171 · see citing works
ROTE: Rollback Protection for Trusted Execution
Matetić, S., Ahmed, M., Kostiainen, K., Dhar, A., Sommer, D., Gervais, A., Juels, A., & Čapkun, S. (2017) · UCL Discovery (University College London) · Cited by 160 · see citing works
Thwarting Cache Side-Channel Attacks Through Dynamic Software Diversity
Crane, S., Homescu, A., Brunthaler, S., et al. (2015) · Network and Distributed System Security Symposium · doi:10.14722/ndss.2015.23264 · Cited by 159 · see citing works
“Ooh Aah... Just a Little Bit” : A Small Amount of Side Channel Can Go a Long Way
Benger, N., van de Pol, J., Smart, N. P., & Yarom, Y. (2014) · Lecture notes in computer science · doi:10.1007/978-3-662-44709-3_5 · Cited by 159 · see citing works
Martin, R., Demme, J., & Sethumadhavan, S. (2012) · ACM SIGARCH Computer Architecture News · doi:10.1145/2366231.2337173 · Cited by 151 · see citing works
Recovering OpenSSL ECDSA Nonces Using the FLUSH+RELOAD Cache Side-channel Attack.Preprint
Yarom, Y., & Benger, N. (2014) · IACR Cryptology ePrint Archive · Cited by 139 · see citing works
Scheduler-based defenses against cross-VM side-channels
Varadarajan, V., Ristenpart, T., & Swift, M. M. (2014) · USENIX Security Symposium · Cited by 138 · see citing works
A Software Approach to Defeating Side Channels in Last-Level Caches
Zhou, Z., Reiter, M. K., & Zhang, Y. (2016) · ACM SIGSAC Conference on Computer and Communications Security (CCS) · doi:10.1145/2976749.2978324 · Cited by 138 · see citing works
Self-citationHigh-Resolution Side Channels for Untrusted Operating Systems
Hähnel, M., Cui, W., & Peinado, M. (2017) · USENIX Annual Technical Conference · Cited by 127 · see citing works
Kuvaiskii, D., Oleksenko, O., Arnautov, S., Trach, B., Bhatotia, P., Felber, P. A., & Fetzer, C. W. (2017) · European Conference on Computer Systems · doi:10.1145/3064176.3064192 · Cited by 119 · see citing works
CacheAudit: A Tool for the Static Analysis of Cache Side Channels.
Doychev, G., Feld, D., Köpf, B., Mauborgne, L., & Reineke, J. (2013) · Cited by 109 · see citing works
Sealed-Glass Proofs: Using Transparent Enclaves to Prove and Sell Knowledge
Tramèr, F., Zhang, F., Lin, H., Hubaux, J., Juels, A., & Shi, E. (2017) · IEEE European Symposium on Security and Privacy · doi:10.1109/eurosp.2017.28 · Cited by 88 · see citing works
SGXIO: Generic Trusted I/O Path for Intel SGX
Weiser, S., & Werner, M. (2017) · Proceedings of the Seventh ACM on Conference on Data and Application Security and Privacy · doi:10.1145/3029806.3029822 · Cited by 79 · see citing works
Ariadne: A Minimal Approach to State Continuity
Strackx, R., & Piessens, F. (2016) · Lirias · Cited by 68 · see citing works
CacheD: Identifying Cache-Based Timing Channels in Production Software
Wang, S., Wang, P., Xiao, L., et al. (2017) · Rare & Special e-Zone (The Hong Kong University of Science and Technology) · Cited by 60 · see citing works
Malware Guard Extension: Using SGX to Conceal Cache AttacksPreprint
Schwarz, M., Weiser, S., Gruss, D., et al. (2017) · arXiv (Cornell University) · doi:10.48550/arxiv.1702.08719 · Cited by 45 · see citing works
Tamrakar, S., Liu, J., Paverd, A., et al. (2017) · ACM Asia Conference on Computer and Communications Security (ASIA CCS) · doi:10.1145/3052973.3053006 · Cited by 33 · see citing works
Sgx-Lapd: Thwarting Controlled Side Channel Attacks via Enclave Verifiable Page Faults
Fu, Y., Bauman, E., Quinonez, R., & Lin, Z. (2017) · Lecture notes in computer science · doi:10.1007/978-3-319-66332-6_16 · Cited by 33 · see citing works
Self-citationDing, Y., Duan, R., Li, L., et al. (2017) · ACM SIGSAC Conference on Computer and Communications Security (CCS) · doi:10.1145/3133956.3138824 · Cited by 24 · see citing works
SGXCrypter: IP protection for portable executables using Intel's SGX technology
Tychalas, D., Tsoutsos, N. G., & Maniatakos, M. (2017) · Asia and South Pacific Design Automation Conference (ASP-DAC) · doi:10.1109/aspdac.2017.7858348 · Cited by 13 · see citing works
Flagged first, then by citations
Research works printed but not linked: 6
- Y. Ding, R. Duan, L. Li, Y. Cheng, Y. Zhang, T. Chen, T. Wei, and H. Wang, "Poster: Rust SGX SDK: Towards memory safety in Intel SGX enclave," in ACM Conference on Computer and Communications Security, 2017.
- D. Kuvaiskii, O. Oleksenko, S. Arnautov, B. Trach, P. Bhatotia, P. Felber, and C. Fetzer, "Sgxbounds: Memory safety for shielded execution," in 12th European Conference on Computer Systems. ACM, 2017.
- G. Maisuradze and C. Rossow, "ret2spec: Speculative execution using return stack buffers," ArXiv e-prints, Jul. 2018.
- R. Martin, J. Demme, and S. Sethumadhavan, "Timewarp: rethinking timekeeping and performance monitoring mechanisms to mitigate side- channel attacks," in 39th Annual International Symposium on Computer Architecture, 2012.
- J. Van Bulck, F. Piessens, and R. Strackx, "SGX-Step: A practical attack framework for precise enclave execution control," in Proceedings of the 2Nd Workshop on System Software for Trusted Execution, ser. SysTEX'17. New York, NY, USA: ACM, 2017, pp. 4:1-4:6.
- F. Zhang, E. Cecchetti, K. Croman, A. Juels, , and E. Shi, "Town crier: An authenticated data feed for smart contracts," in 23rd ACM SIGSAC Conference on Computer and Communications Security. ACM, 2016.
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- Authors
- Chen, G., Chen, S., Xiao, Y., Zhang, Y., Lin, Z., & Lai, T. H.
- Affiliations
- The Ohio State University (US)
- Venue
- 2019 IEEE European Symposium on Security and Privacy (EuroS&P)
- Publisher
- IEEE
- Published
- 2019-06
- Pages
- 142-157
- OpenAlex
- W2807403537
- Cited by
- 319
- References
- 74
- Citations by year
- 2026: 16 · 2025: 36 · 2024: 43 · 2023: 43 · 2022: 41 · 2021: 55 · 2020: 51 · 2019: 25 · 2018: 8 · 2017: 1
- FWCI
- 16.45
- Type
- conference paper
- Language
- en
- Open access
- bronze
- doi.org
- Licence
- Locations
- IEEE European Symposium on Security and Privacy (publishedVersion)
- arXiv (Cornell University) (submittedVersion)
- Funders
- National Science Foundation (1718084, 1750809, 1834215, 1834213)
- Topics
- Physical Sciences › Computer Science › Artificial Intelligence › Security and Verification in Computing
- Physical Sciences › Computer Science › Artificial Intelligence › Cryptographic Implementations and Security
- Physical Sciences › Computer Science › Artificial Intelligence › Cryptography and Data Security
- Keywords
- Intel SGX, Spectre attacks, branch prediction, cache side-channel, symbolic execution
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
What counts as a claim ›How we measure confidence ›How we check this ›
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