The DOI matches its Crossref record; 2 of the 2 references it cites were found in a registry or an index.
Sub 50-nm FinFET: PMOS
Abstract
High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. A 45 nm gate-length PMOS FinEET has an I/sub dsat/ of 410 /spl mu/A//spl mu/m (or 820 /spl mu/A//spl mu/m depending on the definition of the width of a double-gate device) at Vd=Vg=1.2 V and Tox=2.5 nm. The quasi-planar nature of this variant of the double-gate MOSFETs makes device fabrication relatively easy using the conventional planar MOSFET process technologies. Simulation shows possible scaling to 10-nm gate length.
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Citations
Cites
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Hu, C., Bokor, J., King, T.-J., Anderson, E., Kuo, C., Asano, K., Takeuchi, H., Kedzierski, J., Lee, W.-C., & Hisamoto, D. (2000) · IEEE Transactions on Electron Devices · doi:10.1109/16.887014 · Cited by 1,660
Self-citationA folded-channel MOSFET for deep-sub-tenth micron era
Hisamoto, D., Lee, W.-C., Kedzierski, J., Anderson, E., Takeuchi, H., Asano, K., King, T.-J., Bokor, J., & Hu, C. (2002) · International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217) · doi:10.1109/iedm.1998.746531 · Cited by 251
Self-citation
Cited by
Electronics based on two-dimensional materials
Fiori, G., Bonaccorso, F., Iannaccone, G., Palacios, T., Neumaier, D., Seabaugh, A., Banerjee, S. K., & Colombo, L. (2014) · Nature Nanotechnology · doi:10.1038/nnano.2014.207 · Cited by 3,176
Beyond the conventional transistor
Wong, H.-S. P. (2002) · IBM Journal of Research and Development · doi:10.1147/rd.462.0133 · Cited by 573
Ultimately thin double-gate SOI MOSFETs
Ernst, T., Cristoloveanu, S., Ghibaudo, G., Ouisse, T., Horiguchi, S., Ono, Y., Takahashi, Y., & Murase, K. (2003) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2003.811371 · Cited by 245
Investigation of Sidewall High-k Interfacial Layer Effect in Gate-All-Around Structure
Ryu, D., Kim, M., Yu, J., Kim, S., Lee, J.-H., & Park, B.-G. (2020) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2020.2975255 · Cited by 40
Metadata
- Authors
- Huang, X., Lee, W.-C., Kuo, C., Hisamoto, D., Chang, L., Kedzierski, J., Anderson, E., Takeuchi, H., Choi, Y.-K., Asano, K., Subramanian, V., King, T.-J., Bokor, J., & Hu, C.
- Venue
- International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318)
- Publisher
- IEEE
- Published
- 2003-01-22
- Pages
- 67-70
- ISSN
- 0163-1918 (ISSN-L)
- OpenAlex
- W2536886358
- Cited by
- 371
- References
- 2
- FWCI
- 32.92
- Type
- conference paper
- Language
- en
- Open access
- closed
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- Huang, X., Lee, W.-C., Kuo, C., Hisamoto, D., Chang, L., Kedzierski, J., Anderson, E., Takeuchi, H., Choi, Y.-K., Asano, K., Subramanian, V., King, T.-J., Bokor, J., & Hu, C. (2003). Sub 50-nm FinFET: PMOS. International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318). https://doi.org/10.1109/iedm.1999.823848
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