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A neuromorphic visual system using RRAM synaptic devices with Sub-pJ energy and tolerance to variability: Experimental characterization and large-scale modeling
Abstract
We report the use of metal oxide resistive switching memory (RRAM) as synaptic devices for a neuromorphic visual system. At the device level, we experimentally characterized the gradual resistance modulation of RRAM by hundreds of identical pulses. As compared with phase change memory (PCM) reported recently in [1,2], >100×-1000× energy consumption reduction was achieved in RRAM as synaptic devices (<;1 pJ per spike). Based on the experimental results, we developed a stochastic model to quantify the device switching dynamics. At the system level, we simulated the performance of image orientation selectivity on a neuromorphic visual system which consists of 1,024 CMOS neuron circuits and 16,348 RRAM synaptic devices. It was found that the system can tolerate the temporal and spatial variability which are commonly present in RRAM devices, suggesting the feasibility of large-scale hardware implementation of neuromorphic system using RRAM synaptic devices.
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“However, many studies have reported that only two discrete states are demonstrated during potentiation, whereas depression demonstrates multiple states [9-11].”
From Linking Conductive Filament Properties and Evolution to Synaptic Behavior of RRAM Devices for Neuromorphic Applications (2017) · cites this paper as [11]
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Cites
Nanoscale Memristor Device as Synapse in Neuromorphic Systems
Jo, S. H., Chang, T., Ebong, I., Bhadviya, B. B., Mazumder, P., & Lu, W. (2010) · Nano Letters · doi:10.1021/nl904092h · Cited by 4,174
Neuromorphic electronic systems
Mead, C. (1990) · Proceedings of the IEEE · doi:10.1109/5.58356 · Cited by 2,368
Short-term plasticity and long-term potentiation mimicked in single inorganic synapses
Ohno, T., Hasegawa, T., Tsuruoka, T., Terabe, K., Gimzewski, J. K., & Aono, M. (2011) · Nature Materials · doi:10.1038/nmat3054 · Cited by 1,793
Kandel, E. R. 6. E., Schwartz, J. H. (. H., & Jessell, T. M. 6. E. (1985) · Journal of Affective Disorders · doi:10.1016/0165-0327(85)90062-x · Cited by 1,262
Short-Term Memory to Long-Term Memory Transition in a Nanoscale Memristor
Chang, T., Jo, S.-H., & Lu, W. (2011) · ACS Nano · doi:10.1021/nn202983n · Cited by 1,058
Elements of Artificial Neural Networks
Mehrotra, K. G., Mohan, C. K., & Ranka, S. (1996) · The MIT Press eBooks · doi:10.7551/mitpress/2687.001.0001 · Cited by 921
Yu, S., Wu, Y., Jeyasingh, R., Kuzum, D., & Wong, H.-S. P. (2011) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2011.2147791 · Cited by 805
Self-citationOn Spike-Timing-Dependent-Plasticity, Memristive Devices, and Building a Self-Learning Visual Cortex
Zamarreño-Ramos, C., Camuñas-Mesa, L. A., Pérez‐Carrasco, J. A., Masquelier, T., Serrano‐Gotarredona, T., & Linares-Barranco, B. (2011) · Frontiers in Neuroscience · doi:10.3389/fnins.2011.00026 · Cited by 564
Seo, K., Kim, I., Jung, S., Jo, M., Park, S., Park, J., Shin, J., Biju, K. P., Kong, J., Lee, K., et al. (2011) · Nanotechnology · doi:10.1088/0957-4484/22/25/254023 · Cited by 286
A SPICE Compact Model of Metal Oxide Resistive Switching Memory With Variations
Guan, X., Yu, S., & Wong, H. ‐. P. (2012) · IEEE Electron Device Letters · doi:10.1109/led.2012.2210856 · Cited by 283
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Items 101–200 of 213
Fu, K., Luo, S., Fu, H., Hatch, K. A., Alugubelli, S. R., Liu, H., Li, T., Xu, M., Mei, Z., He, Z., et al. (2023) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2023.3321562 · Cited by 21
Reliability-Aware Design Strategies for Stateful Logic-in-Memory Architectures
Zanotti, T., Puglisi, F. M., & Pavan, P. (2020) · IEEE Transactions on Device and Materials Reliability · doi:10.1109/tdmr.2020.2981205 · Cited by 21
SIMPLY: Design of a RRAM-Based Smart Logic-in-Memory Architecture using RRAM Compact Model
Puglisi, F. M., Zanotti, T., & Pavan, P. (2019) · European Solid-State Device Research Conference · doi:10.1109/essderc.2019.8901731 · Cited by 20
Kang, W.-M., Kwon, D., Woo, S. Y., Lee, S., Yoo, H.-N., Kim, J., Park, B., & Lee, J. (2021) · IEEE Access · doi:10.1109/access.2021.3080310 · Cited by 18
Simulation of RRAM memory circuits, a Verilog-A compact modeling approach
González-Cordero, G., Roldán, J. B., & Jiménez-Molinos, F. (2016) · Conference on Design of Circuits and Integrated Systems · doi:10.1109/dcis.2016.7845386 · Cited by 18
RRAM Crossbar-Based In-Memory Computation of Anisotropic Filters for Image Preprocessingloa
Zayer, F., Mohammad, B. S., Saleh, H. H., & Gianini, G. (2020) · IEEE Access · doi:10.1109/access.2020.3004184 · Cited by 18
A High-Performance FPGA Architecture Using One-Level RRAM-Based Multiplexers
Tang, X., Micheli, G. D., & Gaillardon, P. (2016) · IEEE Transactions on Emerging Topics in Computing · doi:10.1109/tetc.2016.2630121 · Cited by 18
Zanotti, T., Pavan, P., & Puglisi, F. M. (2022) · Microelectronic Engineering · doi:10.1016/j.mee.2022.111886 · Cited by 17
Sun, W., Choi, S., Kim, B., & Park, J. (2019) · Materials · doi:10.3390/ma12203451 · Cited by 16
Atomic-scale tuning of ultrathin memristors
Goul, R. W., Marshall, A. D., Seacat, S., Peelaers, H., Hernandez, F. C. R., & Wu, J. Z. (2022) · Communications Physics · doi:10.1038/s42005-022-01037-4 · Cited by 17
A Physics-Informed Recurrent Neural Network for RRAM Modeling
Sha, Y., Lan, J., Li, Y., & Chen, Q. (2023) · Electronics · doi:10.3390/electronics12132906 · Cited by 15
Merged Logic and Memory Fabrics for Accelerating Machine Learning Workloads
Crafton, B., Spetalnick, S. D., Fang, Y., & Raychowdhury, A. (2020) · IEEE Design and Test · doi:10.1109/mdat.2020.3016587 · Cited by 15
Resistive switching memory for high density storage and computing*
Xu, X., Luo, Q., Gong, T., Lv, H., Liu, Q., & Liu, M. (2021) · Chinese Physics B · doi:10.1088/1674-1056/abe0c4 · Cited by 15
Multicore Spiking Neuromorphic Chip in 180-nm With ReRAM Synapses and Digital Neurons
Jiang, H., Lu, J., Zhang, C., Tang, S., An, J., Cheng, L., Lü, J., Wei, J., Zhou, K., Zhang, X., et al. (2023) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2023.3325158 · Cited by 14
Brain-inspired recurrent neural network with plastic RRAM synapses
Milo, V., Chicca, E., & Ielmini, D. (2018) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.2018.8351523 · Cited by 14
Fully Unsupervised Spike-Rate-Dependent Plasticity Learning With Oxide- Based Memory Devices
Kumar, M., Bezugam, S. S., Khan, S., & Suri, M. (2021) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2021.3077346 · Cited by 14
An Efficient Programming Framework for Memristor-based Neuromorphic Computing
Zhang, G. L., Li, B., Huang, X., Shen, C., Zhang, S., Burcea, F., Graeb, H., Ho, T.-Y., Li, H. H., & Schlichtmann, U. (2021) · Design, Automation, and Test in Europe · doi:10.23919/date51398.2021.9474084 · Cited by 14
Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing
Zanotti, T., Pavan, P., & Puglisi, F. M. (2021) · Micromachines · doi:10.3390/mi12101243 · Cited by 14
Post-P&R Performance and Power Analysis for RRAM-Based FPGAs
Tang, X., Giacomin, E., Micheli, G. D., & Gaillardon, P. (2018) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2018.2847600 · Cited by 14
Prabhu, N. L., Loy, D. J., Dananjaya, P. A., Lew, W. S., Toh, E. H., & Raghavan, N. (2020) · Electronics · doi:10.3390/electronics9030414 · Cited by 14
Carbon Nanotubes as Emerging Field Emitters: Influencing Factors and Remedies
Parveen, S., Sarvar, M., Zulfequar, M., & Ali, J. (2025) · Journal of Electronic Materials · doi:10.1007/s11664-024-11682-w · Cited by 13
Dynamic Computing in Memory (DCIM) in Resistive Crossbar Arrays
Motaman, S., & Ghosh, S. (2018) · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · doi:10.1109/iccd.2018.00036 · Cited by 13
Zanotti, T., Puglisi, F. M., & Pavan, P. (2021) · Journal of Low Power Electronics and Applications · doi:10.3390/jlpea11030029 · Cited by 14
Reliability and Performance Analysis of Logic-in-Memory Based Binarized Neural Networks
Zanotti, T., Puglisi, F. M., & Pavan, P. (2021) · IEEE Transactions on Device and Materials Reliability · doi:10.1109/tdmr.2021.3075200 · Cited by 14
Yu, Z., Wang, Z., Bao, S., Ling, Y., Cai, Y., & Huang, R. (2022) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2022.3164630 · Cited by 12
Puglisi, F. M., Deleruyelle, D., Portal, J., Pavan, P., & Larcher, L. (2016) · physica status solidi (a) · doi:10.1002/pssa.201532828 · Cited by 12
Random telegraph noise in HfOx Resistive Random Access Memory: From physics to compact modeling
Puglisi, F. M., Pavan, P., & Larcher, L. (2016) · IEEE International Reliability Physics Symposium proceedings · doi:10.1109/irps.2016.7574624 · Cited by 12
Circuit Reliability of Low-Power RRAM-Based Logic-in-Memory Architectures
Zanotti, T., Puglisi, F. M., & Pavan, P. (2019) · IEEE International Integrated Reliability Workshop final report · doi:10.1109/iirw47491.2019.8989875 · Cited by 12
Kim, M., Kim, S., Bang, S., Kim, T., Lee, D. K., Cho, S., Lee, J., & Park, B. (2017) · Solid-State Electronics · doi:10.1016/j.sse.2017.03.015 · Cited by 12
Graphene-based 3D XNOR-VRRAM with ternary precision for neuromorphic computing
Alimkhanuly, B., Sohn, J., Chang, I., & Lee, S. (2021) · npj 2D Materials and Applications · doi:10.1038/s41699-021-00236-x · Cited by 14
SHINE: A Novel SHA-3 Implementation Using ReRAM-based In-Memory Computing
Nagarajan, K., Ensan, S. S., Khan, M. N. I., Ghosh, S., & Chattopadhyay, A. (2019) · International Symposium on Low Power Electronics and Design (ISLPED) · doi:10.1109/islped.2019.8824979 · Cited by 11
Kim, J., Kim, C.-H., Woo, S. Y., Kang, W.-M., Seo, Y.-T., Lee, S., Oh, S., Bae, J., Park, B., & Lee, J. (2019) · Solid-State Electronics · doi:10.1016/j.sse.2019.107742 · Cited by 11
On-chip trainable hardware-based deep Q-networks approximating a backpropagation algorithm
Kim, J., Kwon, D., Woo, S. Y., Kang, W.-M., Lee, S., Oh, S., Kim, C.-H., Bae, J., Park, B., & Lee, J. (2021) · Neural Computing and Applications · doi:10.1007/s00521-021-05699-z · Cited by 14
Jiang, Y., Huang, P. C., Zhou, Z., & Kang, J. (2019) · Science China Information Sciences · doi:10.1007/s11432-018-9863-6 · Cited by 11
Self-citationRRAM based synaptic devices for neuromorphic visual systems
Kang, J., Gao, B., Huang, P. C., Liu, L. F., Liu, X. Y., Yu, H., Yu, S., & Wong, H. ‐. P. (2015) · IEEE International Conference on Digital Signal Processing (DSP) · doi:10.1109/icdsp.2015.7252074 · Cited by 11
Self-citationCharacterization and Modeling of the Conduction and Switching Mechanisms of HfO x Based RRAM
Yu, S., & Wong, H. ‐. P. (2014) · MRS Proceedings · doi:10.1557/opl.2014.175 · Cited by 10
Self-citationTruong, S. N., Shin, S., Byeon, S.-D., Song, J.-S., Mo, H.-S., & Min, K. (2015) · Nanoscale Research Letters · doi:10.1186/s11671-015-1106-x · Cited by 10
Device variability tolerance of a RRAM-based self-organizing neuromorphic system
Pedró, M., Martin-Martinez, J., Miranda, E. A., Rodriguez, R., Nafria, M., González, M. B., & Campabadal, F. (2018) · IEEE International Reliability Physics Symposium proceedings · doi:10.1109/irps.2018.8353657 · Cited by 9
Akbari, M. K., & Zhuiykov, S. (2021) · ACS Applied Materials & Interfaces · doi:10.1021/acsami.1c17584 · Cited by 10
Design and Application of Oxide-Based Resistive Switching Devices for Novel Computing Architectures
Kang, J., Huang, P. C., Gao, B., Li, H., Chen, Z., Zhao, Y., Liu, C., Liu, L., & Liu, X. (2016) · IEEE Journal of the Electron Devices Society · doi:10.1109/jeds.2016.2577051 · Cited by 9
Self-citationSynaptic device using a floating fin-body MOSFET with memory functionality for neural network
Woo, S. Y., Choi, K.-B., Lim, S., Lee, S., Kim, C.-H., Kang, W.-M., Kwon, D., Bae, J., Park, B., & Lee, J. (2019) · Solid-State Electronics · doi:10.1016/j.sse.2019.02.011 · Cited by 8
Selector-only-memory device using chalcogenide thin film in a 4k crossbar array
Seo, H. K., Jeong, W. H., Jung, J., Park, M. H., Kim, G. H., & Yang, M. (2025) · Materials Science and Engineering R Reports · doi:10.1016/j.mser.2025.101169 · Cited by 8
Behavioral modeling of multilevel HfO2-based memristors for neuromorphic circuit simulation
Pérez-Ávila, A. J., González-Cordero, G., Pérez, E., Quesada, E. P.-B., Mahadevaiah, M. K., Wenger, C., Roldán, J. B., & Jiménez-Molinos, F. (2020) · Conference on Design of Circuits and Integrated Systems · doi:10.1109/dcis51330.2020.9268652 · Cited by 8
Bidirectional Analog Conductance Modulation for RRAM-Based Neural Networks
Jiang, Z., Wang, Z., Zheng, X., Fong, S. W., Qin, S., Chen, H.-Y., Ahn, C., Cao, J., Nishi, Y., Wong, S. S., et al. (2020) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2020.3025849 · Cited by 8
Self-citationPhysics-Based Stochastic Three-Dimensional Modeling for Metal–Oxide Resistive Random Access Memory
Chen, S. (2021) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2021.3082099 · Cited by 8
Harnessing Conductive Oxide Interfaces for Resistive Random-Access Memories
Li, Y., Kvatinsky, S., & Kornblum, L. (2021) · Frontiers in Physics · doi:10.3389/fphy.2021.772238 · Cited by 8
Novel application of spintronics in computing, sensing, storage and cybersecurity
Motaman, S., Khan, M. N. I., & Ghosh, S. (2018) · Design, Automation, and Test in Europe · doi:10.23919/date.2018.8341991 · Cited by 7
Brain-Inspired Memristive Neural Networks for Unsupervised Learning
Ielmini, D., & Milo, V. (2019) · Springer eBooks · doi:10.1007/978-3-319-76375-0_17 · Cited by 6
Smart Logic-in-Memory Architecture For Ultra-Low Power Large Fan-In Operations
Zanotti, T., Puglisi, F., & Pavan, P. (2020) · International Conference on Artificial Intelligence Circuits and Systems · doi:10.1109/aicas48895.2020.9073870 · Cited by 4
Lashkare, S., Uddin, W., Priyadarshi, K., & Ganguly, U. (2023) · Proceedings of the National Academy of Sciences India Section A Physical Sciences · doi:10.1007/s40010-023-00828-w · Cited by 7
Physical understanding and optimization of resistive switching characteristics in oxide-RRAM
Kang, J., Huang, P. C., Chen, Z., Zhao, Y., Liu, C., Han, R., Liu, L. F., Liu, X., Wang, Y. Y., & Gao, B. (2016) · European Solid-State Device Research Conference · doi:10.1109/essderc.2016.7599610 · Cited by 7
Self-citationCircuit Reliability Analysis of In-Memory Inference in Binarized Neural Networks
Zanotti, T., Puglisi, F. M., & Pavan, P. (2020) · IEEE International Integrated Reliability Workshop final report · doi:10.1109/iirw49815.2020.9312858 · Cited by 6
Shen, Y., Shih, Y., Wang, Y., Wang, K., Yang, T., Cyu, R., Yu, Y., & Chueh, Y. (2021) · ACS Materials Letters · doi:10.1021/acsmaterialslett.1c00513 · Cited by 6
A Quantized Training Framework for Robust and Accurate ReRAM-based Neural Network Accelerators
Zhang, C., & Zhou, P. (2021) · Asia and South Pacific Design Automation Conference (ASP-DAC) · doi:10.1145/3394885.3431528 · Cited by 6
Modeling-Based Design of Memristive Devices for Brain-Inspired Computing
Zhao, Y., Chen, R., Huang, P. C., & Kang, J. (2021) · Frontiers in Nanotechnology · doi:10.3389/fnano.2021.654418 · Cited by 7
Self-citationSynaptic Behavior in Metal Oxide-Based Memristors
Hu, P., Wu, S., & Li, S. (2018) · InTech eBooks · doi:10.5772/intechopen.78408 · Cited by 6
Lee, K.-J., Weng, Y.-C., Wang, L.-W., Lin, H.-N., Pal, P., Chu, S.-Y., Lu, D., & Wang, Y.-H. (2022) · Nanomaterials · doi:10.3390/nano12183252 · Cited by 6
Vector-Matrix Multiplier Architecture for In-Memory Computing Applications With RRAM Arrays
Boro, B., Parmar, R., & Trivedi, G. (2025) · IEEE Transactions on Nanotechnology · doi:10.1109/tnano.2025.3560912 · Cited by 5
Review of physics-based compact models for emerging nonvolatile memories
Xu, N., Chen, P.-Y., Wang, J., Choi, W., Lee, K.-H., Jung, E. S., & Yu, S. (2017) · Journal of Computational Electronics · doi:10.1007/s10825-017-1098-0 · Cited by 5
Self-citationReshaping Future Computing Systems With Emerging Nonvolatile Memory Technologies
Chen, Y. (2019) · IEEE Micro · doi:10.1109/mm.2018.2885588 · Cited by 5
Pulse optimization and device engineering of 3D charge-trap flash for synaptic operation
Kumar, M. A., Padovani, A., Larcher, L., Chowdhury, S. M. R., & Baten, M. Z. (2022) · Journal of Applied Physics · doi:10.1063/5.0100173 · Cited by 5
Song, Y., Magyari‐Köpe, B., Lin, Y., & Nishi, Y. (2017) · IEEE International Memory Workshop (IMW) · doi:10.1109/imw.2017.7939089 · Cited by 5
Wu, C., Shen, H., Schroedter, R., Peng, C., Hoffman, H., Slesazeck, S., Tetzlaff, R., Mikolajick, T., & Max, B. (2026) · Advanced Electronic Materials · doi:10.1002/aelm.202500644 · Cited by 4
Vijay, H. M., & Ramakrishnan, V. N. (2021) · Transactions on Electrical and Electronic Materials · doi:10.1007/s42341-021-00374-5 · Cited by 4
Impact of Gate/Drain Biases in FDSOI-Based Analog Synapse on Artificial Neural-Network Performance
Wang, W., Xu, S., Ye, J., Zhao, J., Qu, J., Loubriat, S., Besnard, G., Maleville, C., Weber, O., Arnaud, F., et al. (2025) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2025.3540764 · Cited by 4
Stochastic CBRAM-Based Neuromorphic Time Series Prediction System
Merkel, C. E., Kudithipudi, D., Suri, M., & Wysocki, B. T. (2017) · ACM Journal on Emerging Technologies in Computing Systems · doi:10.1145/2996193 · Cited by 4
LrGAN: A Compact and Energy Efficient PIM-Based Architecture for GAN Training
Mao, H., Shu, J., Song, M., & Li, T. (2020) · IEEE Transactions on Computers · doi:10.1109/tc.2020.3011122 · Cited by 4
Electromagnetic Analysis of Vertical Resistive Memory with a Sub-nm Thick Electrode
Alimkhanuly, B., Kim, S., Kim, L.-W., & Lee, S. (2020) · Nanomaterials · doi:10.3390/nano10091634 · Cited by 4
Synaptic devices based on HfO2 memristors
González, M. B., Maestro-Izquierdo, M., Poblador, S., Zabala, M., Campabadal, F., González-Cordero, G., Aldana, S., Maldonado, D., Jiménez-Molinos, F., & Roldán, J. B. (2021) · Elsevier eBooks · doi:10.1016/b978-0-12-821184-7.00028-1 · Cited by 4
Self-consistent Automated Parameter Extraction of RRAM Physics-Based Compact Model
Zanotti, T., Pavan, P., & Puglisi, F. (2022) · European Solid-State Device Research Conference · doi:10.1109/essderc55479.2022.9947161 · Cited by 4
TaOx-/TiO2-Based Synaptic Devices
Wang, I., & Hou, T. (2017) · Springer eBooks · doi:10.1007/978-3-319-54313-0_4 · Cited by 4
Nonvolatile and Volatile Resistive Switching - Characterization, Modeling, Memristive Subcircuits
Liu, T. (2013) · VTechWorks (Virginia Tech) · Cited by 4
The Future of CMOS : More Moore or a New Disruptive Technology?
El‐Atab, N., & Hussain, M. M. (2018) · Wiley eBooks · doi:10.1002/9783527811861.ch1 · Cited by 4
Time-to-First-Spike Coding in Sensory Neuron for Energy-Efficient Spiking Neural Networks
Lee, J., Hwang, S.-H., Cho, W., Byeon, K.-U., & Han, J. (2025) · IEEE Electron Device Letters · doi:10.1109/led.2025.3580157 · Cited by 3
Memristor based neuromorphic circuit for visual pattern recognition
Lorenzi, P., Sucre, V., Romano, G., Rao, R., & Irrera, F. (2015) · International Conference on Memristive Systems (MEMRISYS) · doi:10.1109/memrisys.2015.7378387 · Cited by 3
Analog synaptic devices applied to spiking neural networks for reinforcement learning applications
Kim, J., Lee, S., Kim, C.-H., Park, B., & Lee, J. (2022) · Semiconductor Science and Technology · doi:10.1088/1361-6641/ac6ae0 · Cited by 3
On-Chip Trainable Spiking Neural Networks Using Time-To-First-Spike Encoding
Im, J., Kim, J., Yoo, H.-N., Baek, J.-W., Kwon, D., Oh, S., Kim, J., Hwang, J., Park, B., & Lee, J. (2022) · IEEE Access · doi:10.1109/access.2022.3160271 · Cited by 3
Variation Tolerant RRAM Based Synaptic Architecture for On-Chip Training
Dongre, A., & Trivedi, G. (2023) · IEEE Transactions on Nanotechnology · doi:10.1109/tnano.2023.3298962 · Cited by 3
Modeling and Simulation of RRAM With Carbon Nanotube Electrode
Wang, D., Zhu, J.-H., Liu, Y., Wang, G., & Zhao, W. (2023) · IEEE Transactions on Nanotechnology · doi:10.1109/tnano.2023.3341414 · Cited by 3
Paskaleva, A., Hudec, B., Jancovic, P., Fröhlich, K., & Spassov, D. (2014) · Facta universitatis - series Electronics and Energetics · doi:10.2298/fuee1404621p · Cited by 3
Kavehei, O., Skafidas, E. S., & Eshraghian, K. (2013) · Springer eBooks · doi:10.1007/978-3-319-02630-5_19 · Cited by 3
iMACE: In-Memory Acceleration of Classic McEliece Encoder
Nagarajan, K., Ensan, S. S., Mandal, S., Ghosh, S., & Chattopadhyay, A. (2019) · IEEE Computer Society Annual Symposium on VLSI · doi:10.1109/isvlsi.2019.00098 · Cited by 3
Wijesinghe, P., Ankit, A., Sengupta, A., & Roy, K. (2017) · arXiv (Cornell University) · doi:10.48550/arxiv.1712.01472 · Cited by 4
Bio-Inspired Artificial Olfactory System
Huang, P.-C. (2015) · eScholarship (California Digital Library) · Cited by 3
Improved Memristor Control using Device Physics and Deep Reinforcement Learning
Yang, M.-J., Yu, Z., Pedretti, G., Neftci, E. O., & Strachan, J. P. (2025) · IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) · doi:10.1109/aicas64808.2025.11173161 · Cited by 2
Software-Hardware Co-Optimization on Partial-Sum Problem for PIM-based Neural Network Accelerator
Wu, Q., Tao, L., Liang, H., Wei, Y., Tian, T., Xue, S., & Jin, X. (2021) · IEEE High Performance Extreme Computing Conference · doi:10.1109/hpec49654.2021.9622798 · Cited by 2
Paskaleva, A., Hudec, B., Jancovic, P., & Fröhlich, K. (2014) · IEEE International Conference on Microelectronics (MIEL) · doi:10.1109/miel.2014.6842144 · Cited by 2
Latif, M. R., Nichol, T., Mitkova, M. I., Tenne, D. A., Csarnovics, I., Kökényesi, S., & Csík, A. (2014) · IEEE Workshop on Microelectronics and Electron Devices (WMED) · doi:10.1109/wmed.2014.6818720 · Cited by 2
Kavehei, O., Skafidas, E. S., & Eshraghian, K. (2019) · Springer eBooks · doi:10.1007/978-3-319-76375-0_35 · Cited by 2
Non-overlapped implantation (NOI) MOSFET synapse and its implementation on supervised neural network
Jeng, E. S., Peng, K., Chou, S. W., Chen, H. X., & Chiang, Y.-L. (2015) · Neurocomputing · doi:10.1016/j.neucom.2015.04.067 · Cited by 2
Reconfigurable and Dense Analog Circuit Design Using Two Terminal Resistive Memory
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Metadata
- Authors
- Yu, S., Gao, B., Fang, Z., Yu, H., Kang, J., & Wong, H.-S. P.
- Affiliations
- Stanford SystemX Alliance (US)
- Peking University (CN)
- Agency for Science, Technology and Research (SG)
- Southern University of Science and Technology (CN)
- Venue
- 2012 International Electron Devices Meeting
- Publisher
- IEEE
- Published
- 2012-12
- Pages
- 10.4.1-10.4.4
- ISSN
- 0163-1918 (ISSN-L)
- OpenAlex
- W1987760418
- Cited by
- 213
- References
- 13
- Citations by year
- 2026: 2 · 2025: 7 · 2024: 4 · 2023: 12 · 2022: 13 · 2021: 23 · 2020: 24 · 2019: 21 · 2018: 29 · 2017: 21 · 2016: 19 · 2015: 15 · 2014: 13 · 2013: 10
- FWCI
- 15.52
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- Technical digest - International Electron Devices Meeting/Technical digest (publishedVersion)
- Funders
- National Science Foundation
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Computer Science › Artificial Intelligence › Neural Networks and Reservoir Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Ferroelectric and Negative Capacitance Devices
- Keywords
- resistive random access memory, metal oxide memory, energy-efficient neuromorphic hardware
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