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NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures
Abstract
NeuroSim+ is an integrated simulation framework for benchmarking synaptic devices and array architectures in terms of the system-level learning accuracy and hardware performance metrics. It has a hierarchical organization from the device level (transistor technology and memory cell models) to the circuit level (synaptic array architectures and neuron periphery) and then to the algorithm level (neural network topologies). In this work, we study the impact of the “analog” eNVM non-ideal device properties and benchmark the trade-offs of SRAM, digital and analog eNVM based array architectures for online learning and offline classification. The source code of NeuroSim+ version 1.0 is publicly available at https ://github. co m/neuro sim/MLP Neuro Sim.
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Self-citationUnderstanding memristive switching via in situ characterization and device modeling
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XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks
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Metadata
- Authors
- Chen, P.-Y., Peng, X., & Yu, S.
- Venue
- 2017 IEEE International Electron Devices Meeting (IEDM)
- Publisher
- IEEE
- Published
- 2017-12
- Pages
- 6.1.1-6.1.4
- ISSN
- 0163-1918 (ISSN-L)
- OpenAlex
- W2787759178
- Cited by
- 435
- References
- 10
- FWCI
- 44.36
- Type
- conference paper
- Language
- en
- Open access
- closed
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