The DOI matches its Crossref record; 2 of the 2 references it cites were found in a registry or an index.
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory
Abstract
Various new nonvolatile memory (NVM) technologies have emerged recently. Among all the investigated new NVM candidate technologies, spin-torque-transfer memory (STT-RAM, or MRAM), phase-change random-access memory (PCRAM), and resistive random-access memory (ReRAM) are regarded as the most promising candidates. As the ultimate goal of this NVM research is to deploy them into multiple levels in the memory hierarchy, it is necessary to explore the wide NVM design space and find the proper implementation at different memory hierarchy levels from highly latency-optimized caches to highly density- optimized secondary storage. While abundant tools are available as SRAM/DRAM design assistants, similar tools for NVM designs are currently missing. Thus, in this paper, we develop NVSim, a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies.
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Cites
Memristive switching mechanism for metal/oxide/metal nanodevices
Yang, J. J., Pickett, M. D., Li, X., Ohlberg, D. A. A., Stewart, D. R., & Williams, R. S. (2008) · Nature Nanotechnology · doi:10.1038/nnano.2008.160 · Cited by 2,987
Nanoscale resistive memory with intrinsic diode characteristics and long endurance
Kim, K.-H., Hyun Jo, S., Gaba, S., & Lu, W. (2010) · Applied Physics Letters · doi:10.1063/1.3294625 · Cited by 187
Cited by
Memristive devices for computing
Yang, J. J., Strukov, D. B., & Stewart, D. R. (2013) · Nature Nanotechnology · doi:10.1038/nnano.2012.240 · Cited by 3,885
PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning
Song, L., Qian, X., Li, H., & Chen, Y. (2017) · 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA) · doi:10.1109/hpca.2017.55 · Cited by 833
Hardware implementation of memristor-based artificial neural networks
Aguirre, F., Sebastian, A., Le Gallo, M., Song, W., Wang, T., Yang, J. J., Lu, W., Chang, M.-F., Ielmini, D., Yang, Y., et al. (2024) · Nature Communications · doi:10.1038/s41467-024-45670-9 · Cited by 564
Chen, P.-Y., Peng, X., & Yu, S. (2017) · 2017 IEEE International Electron Devices Meeting (IEDM) · doi:10.1109/iedm.2017.8268337 · Cited by 435
MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems
Zhu, Z., Sun, H., Qiu, K., Xia, L., Krishnan, G., Dai, G., Niu, D., Chen, X., Hu, X. S., Cao, Y., et al. (2020) · Proceedings of the 2020 on Great Lakes Symposium on VLSI · doi:10.1145/3386263.3407647 · Cited by 77
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Metadata
- Authors
- Dong, X., Xu, C., Xie, Y., & Jouppi, N. P.
- Venue
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Published
- 2012-07
- Volume
- 31
- Issue
- 7
- Pages
- 994-1007
- ISSN
- 0278-0070 (ISSN-L)
- 1937-4151
- OpenAlex
- W2010202670
- Cited by
- 1,217
- References
- 2
- FWCI
- 41.51
- Type
- journal article
- Language
- en
- Open access
- closed
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- CoChat. (2026). Citation check: NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory. https://app.cochat.ai/papers/10.1109/tcad.2012.2185930
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- Dong, X., Xu, C., Xie, Y., & Jouppi, N. P. (2012). NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. https://doi.org/10.1109/tcad.2012.2185930
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