Ferroelectric FET analog synapse for acceleration of deep neural network training
Abstract
The memory requirement of at-scale deep neural networks (DNN) dictate that synaptic weight values be stored and updated in off-chip memory such as DRAM, limiting the energy efficiency and training time. Monolithic cross-bar / pseudo cross-bar arrays with analog non-volatile memories capable of storing and updating weights on-chip offer the possibility of accelerating DNN training. Here, we harness the dynamics of voltage controlled partial polarization switching in ferroelectric-FETs (FeFET) to demonstrate such an analog synapse. We develop a transient Presiach model that accurately predicts minor loop trajectories and remnant polarization charge (Pr) for arbitrary pulse width, voltage, and history. We experimentally demonstrate a 5-bit FeFET synapse with symmetric potentiation and depression characteristics, and a 45x tunable range in conductance with 75ns update pulse. A circuit macro-model is used to evaluate and benchmark on-chip learning performance (area, latency, energy, accuracy) of FeFET synaptic core revealing a 103to 106acceleration in online learning latency over multi-state RRAM based analog synapses.
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These techniques can be more generally applied to other non-volatile resistive memory technologies such as phase-change memory, magnetoresistive RAM and ferroelectric field-effect transistors.
“These techniques can be more generally applied to other non-volatile resistive memory technologies such as phase-change memory8,17,21,23,24, magnetoresistive RAM48 and ferroelectric field-effect transistors49.”
From A compute-in-memory chip based on resistive random-access memory (2022) · cites this paper as [49]
The proposed VMM accelerator achieves a smaller footprint compared to [32], [33], [34], and [35].
“whereas our proposed VMM accelerator achieves a smaller footprint compared to [32], [33], [34], and [35].”
From Framework for In-Memory Computing Based on Memristor and Memcapacitor for On-Chip Training (2023) · cites this paper as [33]
Cites
Nanoscale Memristor Device as Synapse in Neuromorphic Systems
Jo, S. H., Chang, T., Ebong, I., Bhadviya, B. B., Mazumder, P., & Lu, W. (2010) · Nano Letters · doi:10.1021/nl904092h · Cited by 4,174 · cited 6× · see citing works
“increased learning accuracy Ideal [4] [5]”
BackgroundInfluentialWoo, J., Moon, K., Song, J., Lee, S., Kwak, M., Park, J., & Hwang, H. (2016) · IEEE Electron Device Letters · doi:10.1109/led.2016.2582859 · Cited by 512 · cited 6× · see citing works
“[2] J. Woo, et al., “Improved synaptic behavior under identical pulses using AlOx/HfO2 bilayer RRAM array for neuromorphic systems,” IEEE Electron Device Lett., 37, 8, 994–997, 2016.”
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Neuro-Inspired Computing With Emerging Nonvolatile Memorys
Yu, S. (2018) · Proceedings of the IEEE · doi:10.1109/jproc.2018.2790840 · Cited by 1,170 · see citing works
Self-citationA compute-in-memory chip based on resistive random-access memory
Wan, W., Kubendran, R., Schaefer, C., Eryilmaz, S. B., Zhang, W., Wu, D., Deiss, S., Raina, P., Qian, H., Gao, B., et al. (2022) · Nature · doi:10.1038/s41586-022-04992-8 · Cited by 943 · see citing works
Peng, X., Huang, S., Jiang, H., Lu, A., & Yu, S. (2021) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2020.3043731 · Cited by 317 · see citing works
Self-citationPerspective: A review on memristive hardware for neuromorphic computation
Sung, C., Hwang, H., & Yoo, I. K. (2018) · Journal of Applied Physics · doi:10.1063/1.5037835 · Cited by 217 · see citing works
Ning, H., Yu, Z., Zhang, Q., Wen, H., Gao, B., Mao, Y., Li, Y., Zhou, Y., Zhou, Y., Chen, J., et al. (2023) · Nature Nanotechnology · doi:10.1038/s41565-023-01343-0 · Cited by 198 · see citing works
Sun, X., & Yu, S. (2019) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2019.2933148 · Cited by 170 · see citing works
Self-citationStrategies to Improve the Accuracy of Memristor-Based Convolutional Neural Networks
Pan, W.-Q., Chen, J., Kuang, R., Li, Y., He, Y.-H., Feng, G.-R., Duan, N., Chang, T.-C., & Miao, X.-S. (2020) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2019.2963323 · Cited by 76 · see citing works
Framework for In-Memory Computing Based on Memristor and Memcapacitor for On-Chip Training
Singh, A., & Lee, B.-G. (2023) · IEEE Access · doi:10.1109/access.2023.3324375 · Cited by 19 · see citing works
- Authors
- Jerry, M., Chen, P.-Y., Zhang, J., Sharma, P., Ni, K., Yu, S., & Datta, S.
- Affiliations
- University of Notre Dame (US)
- Arizona State University (US)
- Venue
- 2017 IEEE International Electron Devices Meeting (IEDM)
- Publisher
- IEEE
- Published
- 2017-12
- Pages
- 6.2.1-6.2.4
- ISSN
- 0163-1918 (ISSN-L)
- OpenAlex
- W2787453651
- Cited by
- 599
- References
- 2
- Citations by year
- 2026: 41 · 2025: 65 · 2024: 63 · 2023: 98 · 2022: 103 · 2021: 86 · 2020: 79 · 2019: 49 · 2018: 15
- FWCI
- 55.33
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- Technical digest - International Electron Devices Meeting/Technical digest (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Ferroelectric and Negative Capacitance Devices
- Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
- Keywords
- ferroelectric field-effect transistors, analog synapses, deep neural network training, remnant polarization, conductance tuning, synaptic potentiation and depression
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Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
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