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Analysis of timing jitter in CMOS ring oscillators

Weigandt, T.C., Beomsup Kim, Gray, P.R.·2002·Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94

Abstract

in this paper the effects of thermal noise in transistors on timing jitter in CMOS ring-oscillators composed of source-coupled differential resistively-loaded delay cells is investigated. The relationship between delay element design parameters and the inherent thermal noise-induced jitter of the generated waveform are analyzed. These results are compared with simulated results from a Monte-Carlo analysis with good agreement. The analysis shows that timing jitter is inversely proportional to the square root of the total capacitance at the output of each inverter, and inversely proportional to the gate-source bias voltage above threshold of the source-coupled devices in the balanced state. Furthermore, these dependencies imply an inverse relationship between jitter and power consumption for an oscillator with fixed output period. Phase noise and timing jitter performance are predicted to improve at a rate of 10 dB per decade increase in power consumption.>

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Crossref · 10.1109/iscas.1994.409188

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Metadata

Authors
Weigandt, T. C., Kim, B., & Gray, P. R.
Venue
Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94
Publisher
IEEE
Published
2002-12-17
Volume
4
Pages
27-30
ISSN
0271-4302 (ISSN-L)
OpenAlex
W1585651733
Cited by
286
References
1
FWCI
28.84
Type
conference paper
Language
en
Open access
closed

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CoChat. (2026). Citation check: Analysis of timing jitter in CMOS ring oscillators. https://app.cochat.ai/papers/10.1109/iscas.1994.409188
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Weigandt, T. C., Kim, B., & Gray, P. R. (2002). Analysis of timing jitter in CMOS ring oscillators. Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94. https://doi.org/10.1109/iscas.1994.409188

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