15.1 A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing

Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks

Chen, Y.-H., Krishna, T., Emer, J. S., & Sze, V. (2017) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2016.2616357 · Cited by 3,247

14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks

Chen, Y., Krishna, T., Emer, J., & Sze, V. (2016) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.2016.7418007 · Cited by 713

15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications

Dong, Q., Sinangil, M. E., Erbagci, B., Sun, D., Khwa, W.-S., Liao, H.-J., Wang, Y., & Chang, J. (2020) · 2020 IEEE International Solid- State Circuits Conference - (ISSCC) · doi:10.1109/isscc19947.2020.9062985 · Cited by 346

A 64-Tile 2.4-Mb In-Memory-Computing CNN Accelerator Employing Charge-Domain Compute

Valavi, H., Ramadge, P. J., Nestler, E., & Verma, N. (2019) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2019.2899730 · Cited by 328

A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing

Jia, H., Valavi, H., Tang, Y., Zhang, J., & Verma, N. (2020) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2020.2987714 · Cited by 233

An always-on 3.8μJ/86% CIFAR-10 mixed-signal binary CNN processor with all memory on chip in 28nm CMOS

Bankman, D. J., Yang, L., Moons, B., Verhelst, M., & Murmann, B. (2018) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.2018.8310264 · Cited by 158

14.2 A Compute SRAM with Bit-Serial Integer/Floating-Point Operations for Programmable In-Memory Vector Acceleration

Wang, J., Wang, X., Eckert, C. A., Subramaniyan, A. K., Das, R., Blaauw, D. T., & Sylvester, D. (2019) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.2019.8662419 · Cited by 141

14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse

Yue, J., Yuan, Z., Feng, X., He, Y., Zhang, Z., Si, X., Liu, R., Chang, M., Li, X., Yang, H., et al. (2020) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc19947.2020.9062958 · Cited by 141

A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS

Guo, R., Liu, Y., Zheng, S., Wu, S.-Y., Ouyang, P., Khwa, W.-S., Chen, X., Chen, J., Li, X., Liu, L., et al. (2019) · Symposium on VLSI Circuits · doi:10.23919/vlsic.2019.8778028 · Cited by 101

7.2 A 12nm Programmable Convolution-Efficient Neural-Processing-Unit Chip Achieving 825TOPS

Jiao, Y., Han, L., Jin, R., Yi-Jung, S., Ho, C., Li, Y., Li, Y., Chen, L., Chen, Z., Liu, L., et al. (2020) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc19947.2020.9062984 · Cited by 59

Hidden-ROM

Chen, Y., Yin, G., Lee, M., Tang, W., Yang, Z., Liu, Y., Yang, H., & Li, X. (2022) · International Conference on Computer Aided Design · doi:10.1145/3508352.3549335 · Cited by 4

A 28-nm 3.32-nJ/Frame Compute-in-Memory CNN Processor With Layer Fusion for Always-on Applications

Zhao, Y., He, P., Zhu, Y., Martins, R. P., Chan, C., & Zhang, M. (2025) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2025.3542590 · Cited by 6

SRAM-Based Processing-in-Memory (PIM)

Kim, H., Yu, C., & Kim, B. (2022) · Springer eBooks · doi:10.1007/978-3-030-98781-7_3 · Cited by 4

ISSA

Lo, Y.-C., Yeh, C.-C., Wu, J.-S., Wang, C., Tsai, Y.-C., Ting, W.-C., & Liu, R.-S. (2022) · International Conference on Computer Aided Design · doi:10.1145/3508352.3549333 · Cited by 4

Guarding Deep Learning Systems With Boosted Evasion Attack Detection and Model Update

Chen, X., Halder, D., Islam, K. M., & Ray, S. (2023) · IEEE Internet of Things Journal · doi:10.1109/jiot.2023.3324568 · Cited by 4

IMAGINE: An 8-to-1b 22nm FD-SOI Compute-In-Memory CNN Accelerator With an End-to-End Analog Charge-Based 0.15-8POPS/W Macro Featuring Distribution-Aware Data Reshaping

Kneip, A., Lefebvre, M., Maistriaux, P., & Bol, D. (2025) · IEEE transactions on circuits and systems for artificial intelligence. · doi:10.1109/tcasai.2025.3576323 · Cited by 4

Statistical computing framework and demonstration for in-memory computing systems

Zhang, B., Deaville, P., & Verma, N. (2022) · ACM/IEEE Design Automation Conference (DAC) · doi:10.1145/3489517.3530557 · Cited by 4

Optimization Strategies for Digital Compute-in-Memory from Comparative Analysis with Systolic Array

Li, W., Lee, J., & Yu, S. (2023) · IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) · doi:10.1109/aicas57966.2023.10168651 · Cited by 4

A Multichiplet Computing-in-Memory Architecture Exploration Framework Based on Various CIM Devices

Dai, Z., Xiang, F., Fu, X., He, Y., Sun, W., Liu, Y., Yang, G., Zhang, F., Yue, J., & Li, L. (2024) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2024.3416256 · Cited by 4

Cache-PIM: An ECC-Compatible eDRAM Processing-in-Memory for Last-Level Cache With Triple-Level Error Correction

Ha, S., Um, S., Kim, S., Sohn, K., & Yoo, H. (2025) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2025.3568485 · Cited by 3

COMPASS: A Compiler Framework for Resource-Constrained Crossbar-Array Based In-Memory Deep Learning Accelerators

Park, J., Choe, J., Kim, D., & Kim, J. (2025) · Design, Automation, and Test in Europe · doi:10.23919/date64628.2025.10993229 · Cited by 3

CAPC: A Configurable Analog Pop-Count Circuit for Near-Memory Binary Neural Networks

Jebali, F., Majumdar, A., Laborieux, A., Hirtzlin, T., Vianello, E., Walder, J.-P., Bocquet, M., Querlioz, D., & Portal, J. (2021) · IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) · doi:10.1109/mwscas47672.2021.9531919 · Cited by 3

Energy-Efficient Sensor Platform using Reliable Analog-to-Feature Extraction

Lee, M., Sharma, S. K., Wang, W.-C., & Mukhopadhyay, S. (2023) · Proceedings of IEEE Sensors/Proceedings of IEEE Sensors ... · doi:10.1109/sensors56945.2023.10324915 · Cited by 3

A 1.1-nJ/Classification True Analog Current Computing on Multilayer Neural Network With Crystalline-IGZO/Si-CMOS Monolithic Stack Technology

Tsuda, K., Furutani, K., Yakubo, Y., Godo, H., Ando, Y., Kosuge, A., Nakura, T., & Yamazaki, S. (2024) · IEEE Journal of the Electron Devices Society · doi:10.1109/jeds.2024.3439712 · Cited by 3

Neural Network Training on In-Memory-Computing Hardware With Radix-4 Gradients

Grimm, C., & Verma, N. (2022) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2022.3185556 · Cited by 5

Design Methodology and Trends of SRAM-Based Compute-in-Memory Circuits

Dong, F., Si, X., & Chang, M. (2022) · IEEE International Conference on Solid-State and Integrated Circuit Technology · doi:10.1109/icsict55466.2022.9963239 · Cited by 3

Training Neural Networks With In-Memory-Computing Hardware and Multi-Level Radix-4 Inputs

Grimm, C., Lee, J., & Verma, N. (2024) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2024.3360052 · Cited by 3

Cambricon-M: A Fibonacci-Coded Charge-Domain SRAM-Based CIM Accelerator for DNN Inference

Guo, H., Zou, M., Hao, Y., Du, Z., Ren, E., Liu, Y., Zhao, Y., Ma, T., Zhang, R., Hu, X., et al. (2024) · IEEE/ACM International Symposium on Microarchitecture (MICRO) · doi:10.1109/micro61859.2024.00121 · Cited by 3

Kung-Fu: An Energy-Efficient Compute-In-Memory Approach for Neural Network Inference Using Multi-Level Binary Computing Fusion

Liao, T., Chen, Y., Tang, W., Chen, Z., Wang, Y., Yang, H., & Li, X. (2025) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas56072.2025.11043740 · Cited by 2

A Reconfigurable SRAM Computing-in-Memory Macro Supporting Ping-Pong Operation and CIM pipeline for Multi-mode MAC operations

Xiao, K., Cui, X., Qiao, X., Wang, X., & Wang, Y. (2022) · IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) · doi:10.1109/icta56932.2022.9962978 · Cited by 2

Hierarchical Non-Structured Pruning for Computing-In-Memory Accelerators with Reduced ADC Resolution Requirement

Xue, W., Bai, J., Sun, S., & Kang, W. (2023) · Design, Automation, and Test in Europe · doi:10.23919/date56975.2023.10136975 · Cited by 2

A 332 TOPS/W Input/Weight-Parallel Computing-in-Memory Processor with Voltage-Capacitance-Ratio Cell and Time-Based ADC

Hong, S., Um, S., Kim, S., Kim, S., Jo, W., & Yoo, H. (2023) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas46773.2023.10181902 · Cited by 2

131TOPS/W 8b ACIM Exploiting Weight-Embedded Auto-Accumulation and Supporting Symmetric Quantization Networks

He, W., Bai, P., Luo, H., Jin, Z., Wu, H., Zhang, J.-Y., Chao, X., Liu, H., He, Y., & Li, Q. (2024) · Custom Integrated Circuits Conference · doi:10.1109/cicc60959.2024.10529000 · Cited by 2

ISSA: Architecting CNN Accelerators Using Input-Skippable, Set-Associative Computing-in-Memory

Lo, Y.-C., Wu, J.-S., Wang, C., Tsai, Y.-C., Yeh, C.-C., Ting, W.-C., & Liu, R.-S. (2024) · IEEE Transactions on Computers · doi:10.1109/tc.2024.3404060 · Cited by 2

A 16nm 128kB high-density fully digital In Memory Compute macro with reverse SRAM pre-charge achieving 0.36TOPs/mm2, 256kB/mm2 and 23. 8TOPs/W

Jiang, W., Houshmand, P., Verhelst, M., & Dehaene, W. (2023) · European Solid-State Circuits Conference (ESSCIRC) · doi:10.1109/esscirc59616.2023.10268774 · Cited by 2

A Capacitor-Saver Redundant SAR ADC to Optimize Readout in Compute In-Memory Systems

Ahrar, A., Makhlooghpoor, A., Lu, X., Xu, J., Azghadi, M. R., Kassiri, H., & Amirsoleimani, A. (2025) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas56072.2025.11043833 · Cited by 1

SRAM-Centric In-Memory Computing for Artificial Intelligence and Neural Network Applications

Sharma, K., Ahir, J., & Singh, L. (2025) · IEEE World Conference on Applied Intelligence and Computing (AIC) · doi:10.1109/aic66080.2025.11212090 · Cited by 1

A Scalable 1L2D Multi-Core Near-DRAM Computing Accelerator Based on 3D Hybrid Bonding for AI Models

Han, Z., Cao, Y., Xuanzhi, L. I. U., CHENG, J., & Jianguo, Y. A. N. G. (2025) · IEICE Transactions on Electronics · doi:10.1587/transele.2025ecp5020 · Cited by 1

Scoping the Landscape of (Extreme) Edge Machine Learning Processors

Jain, V., & Verhelst, M. (2023) · Springer eBooks · doi:10.1007/978-3-031-38230-7_3 · Cited by 3

Software-defined process-near-memory architecture using 3D hybrid bonding integration

Xu, A., Deng, C., Zhu, J., Wang, Y., Wei, S., & Liu, L. (2024) · Science China Information Sciences · doi:10.1007/s11432-023-3965-1 · Cited by 1

A 107 TOPS/W Instruction Controlled Scalable 8b Precision Analog In-Memory Computing Core with Flexible Kernel Routing for Embedded Applications

Kundu, B. K., Müller, R., Patil, Y. R., & Brederlow, R. (2025) · IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) · doi:10.1109/aicas64808.2025.11173108 · Cited by 1

Domino: A Tailored Network-on-Chip Architecture to Enable Highly Localized Inter- and Intra-Memory DNN ComputingPreprint

Zhou, K., He, Y., Xiao, R., & Huang, K. (2021) · arXiv (Cornell University) · doi:10.48550/arxiv.2107.09500 · Cited by 1

Hardware and algorithm co-optimization for energy-efficient machine learning integrated circuits

Kim, H. (2022) · doi:10.32657/10356/168401 · Cited by 1

An 8T and 10T static random access memory with bit-serial operations for in-memory computingPreprint

Xu, W., Lou, M., Li, L., Zhang, K., & Gong, L. (2023) · Research Square · doi:10.21203/rs.3.rs-3758835/v1 · Cited by 1

Challenges and Opportunities of Energy-Efficient CIM SoC Design for Edge AI Devices

Yue, J., Sun, W., Yang, H., & Liu, Y. (2021) · International SoC Design Conference · doi:10.1109/isocc53507.2021.9613846

Mixed-Signal Compute and Memory Fabrics for Deep Neural Networks

Murmann, B. (2022) · Springer eBooks · doi:10.1007/978-3-030-91741-8_1

Computing-in-memory circuits and cross-layer integrated design and optimization: from SRAM to FeFET

尹, 勋., 岳, 金., 黄, 庆., 李, 超., 蔡, 嘉., 杨, 泽., 卓, 成., & 刘, 明. (2022) · Scientia Sinica Informationis · doi:10.1360/ssi-2021-0420 · Cited by 1

A 8.5 fJ/Addition Dynamic Analog 8-3 Compressor for Energy Efficient Computing-in-Memory Macros

Li, P., Zhang, J., Jiang, W., & Chen, C. (2022) · IEEE International Conference on Solid-State and Integrated Circuit Technology · doi:10.1109/icsict55466.2022.9963267

Women in Circuits [Guest Editorial]

Gu, Q. J. (2022) · IEEE Solid-State Circuits Magazine · doi:10.1109/mssc.2022.3207334

GERALT: Real-time Detection of Evasion Attacks in Deep Learning Systems

Chen, X., & Ray, S. (2023) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas46773.2023.10181921

Time-domain Subtractive Readout Scheme for Scalable Capacitive Analog In-Memory Computing

Oshio, R., Kuwahara, T., Kimura, M., & Nakashima, Y. (2023) · IEEE International System-on-Chip Conference (SOCC) · doi:10.1109/socc58585.2023.10256918

Decoupling efficiency-performance optimization for modern neural networks

Jin, Q. (2023) · Digital Repository Service (Northeastern University) · doi:10.17760/d20592335

Design and Performance Analysis of a [8/8/8] Charge Domain Mixed-Signal Multiply-Accumulator

Matsuzawa, A., Alonso, A. M., & Miyahara, M. (2023) · Electronics · doi:10.3390/electronics13010050

BFP-CIM: Data-Free Quantization with Dynamic Block-Floating-Point Arithmetic for Energy-Efficient Computing-In-Memory-based Accelerator

Chang, C.-Y., Huang, C.-T., Chuang, Y.-C., Chou, K.-C., & Wu, A.-Y. A. (2024) · Asia and South Pacific Design Automation Conference (ASP-DAC) · doi:10.1109/asp-dac58780.2024.10473797

Assessing the Dynamics of Data Processing

Левин, С. М. (2024) · Computer Engineering and Intelligent Systems · doi:10.7176/ceis/15-1-05

NoPIM: Functional Network-on-Chip Architecture for Scalable High-Density Processing-in-Memory-based Accelerator

Kim, S., Li, Z., Um, S., Jo, W., Ha, S., Kim, S., & Yoo, H. (2024) · IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) · doi:10.1109/coolchips61292.2024.10531178

Basics and Research Status of Neural Network Processors

Yue, J. (2024) · Springer theses · doi:10.1007/978-981-97-3477-1_2

Ultra-Low Power Neural Network Processors using Analog-Based Computation

Fuketa, H. (2024) · International Conference on Integrated Circuits, Design, and Verification (ICDV) · doi:10.1109/icdv61346.2024.10616823

A Bandwidth-Adaptive On-Chip Storage Network Architecture

Wang, K., Yu, N., Tian, D., Yang, L., Wang, P., & Xie, M. (2024) · International Conference on Integrated Circuits and Microsystems (ICICM) · doi:10.1109/icicm63644.2024.10814258

NexusCIM: High-Throughput Multi-CIM Array Architecture with C-Mesh NoC and Hub Cores

Kim, H., & Ryu, S. (2024) · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · doi:10.1109/iccd63220.2024.00068

Energy-Efficient and Reliable Sensor Platform Based on Analog-to-Feature Extraction

Lee, M., Sharma, S. K., Wang, W.-C., Cherukuri, S., & Mukhopadhyay, S. (2025) · IEEE transactions on circuits and systems for artificial intelligence. · doi:10.1109/tcasai.2025.3547316

A Full-system, Programmable, and Extensible In-Memory Computing Simulation Framework for Deep Learning

Zhou, K., Huang, J., Kim, N. S., & Shanbhag, N. R. (2025) · ACM/IEEE Design Automation Conference (DAC) · doi:10.1109/dac63849.2025.11132463 · Cited by 1

Automatic Verification of Analog and Mixed-Signal Neural Network Accelerators and Matrix Multipliers

Müller, R., Kundu, B., Vieregge, J. M., Patil, Y., & Brederlow, R. (2025) · IEEE Nordic Circuits and Systems Conference (NorCAS) · doi:10.1109/norcas66540.2025.11231195

PAR-CIM: A Precise/Approximate Reconfigurable Digital CIM Macro with 0.35-4b Fractional Mixed-Bitwidth Quantization

Zhang, H., Xue, Z., Yi, W., Bai, T., Tan, L., Gu, J., Ding, W., Kang, W., & Pan, B. (2025) · 2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD) · doi:10.1109/iccad66269.2025.11240963

Analyzing Embedded Non-Volatile Memory and Technology Optimizations for In-Memory Computing

Deaville, P., Zhang, B., & Verma, N. (2025) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2025.3632212

A Novel SRAM In-Memory Computing Accelerator Design Approach with R2R-Ladder for AI Sensors and Eddy Current Testing

Becker, K., Zimmerling, M., Landwehr, M., Koster, D., Herrmann, H., & Fischer, W. (2026) · AI Sensors · doi:10.3390/aisens2010002

A 71 TOPS/W 24.2 TOPS/mm 2 14nm SRAM CIM Macro with a Capacitor-less ADC for Edge AI

Chen, Z., Jia, S., & Chen, C. (2025) · IEEE International Conference on ASIC (ASICON) · doi:10.1109/asicon66040.2025.11325953

SPIDER: A Sparsity-Aware High-Density Compute-in-ROM Architecture for Large-Scale Neural Networks On-Chip Deployment

Liao, T., Yu, T., Chen, Y., Yi, T., Wang, Y., Yang, H., & Li, X. (2025) · doi:10.1109/ccmcc67628.2025.11380409

A 28-nm 16-Kb SRAM Computing-in-Memory Macro With Dual Bitline Computing for Boolean Logic Operation and BWN MAC Operation

Lu, W., Xiang, L., Wang, T., Wang, S., Peng, C., Lin, Z., & Wu, X. (2026) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2026.3662417

Cambricon-CIM: Enabling Energy-Efficient and Error-Resilient Analog CIM Acceleration via Reformation of Coding Bases

Guo, H., Ma, T., Du, Z., Zou, M., Hao, Y., Zhao, Y., Zhang, R., Li, W., Hu, X., XU, Z., et al. (2026) · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · doi:10.1109/hpca68181.2026.11408520

A 28-nm System-in-One-Macro Computing-in-Memory Chip Utilizing Leakage-Eliminated 2T1C and Capacitor-Over-Logic 1T1C eDRAM

Qian, Z., Cong, Z., Yan, S., Guo, Z., Dai, Z., He, Y., Sun, W., Dou, C., Zhang, F., Geng, D., et al. (2026) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2026.3684971

Reconfigurable In-Memory Computing With Compute-Fusion SAR ADC for Area-Efficient Pipelined MAC Operations

Yan, S., Wang, J. J., Liu, S., Liu, Y., Wang, Y., Wu, Z. Q., Mao, H. D., Wang, X. R., Chen, T., & Liu, Y. (2026) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2026.3689104

Implementation of SRAM based in-memory computing-architecture for enhancing computational throughput and improving energy efficiency

Sharma, K., Ahir, J., & Singh, L. (2026) · AIP conference proceedings · doi:10.1063/5.0327347

GCC-CIM: A Charge-Domain Compute-in-Memory Macro using Grouped-Row Capacitors and C-2C Ladder with Improved Multi-Bit MAC Linearity

Wang, T., Ren, E., Fang, D. Z., Luo, L., Wei, Q., & Qiao, F. (2026) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas66217.2026.11562463

SuperCIM: A Charge-domain CIM with 3D Parallelism Reconfigurability based on Asynchronous NoC Protocol

Ran, Y., Chen, T., Xu, B., & Pan, B. (2026) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas66217.2026.11562724

Accelerating Automotive Perception: An Outlook on Smart Sensing and Edge AI Trends

Capogrosso, L., & Magno, M. (2026) · IEEE International Workshop on Metrology for Automotive (MetroAutomotive) · doi:10.1109/metroautomotive69354.2026.11644634

Hardware-Aware Neural Network Deployment on Multi-Core in-Memory Computing Systems: A Compiler Perspective

Deng, K., Sun, S., Liu, H., Qin, H., & Kang, W. (2026) · IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) · doi:10.1109/nvmsa71223.2026.11658873

A 28-nm Versatile TinyML SoC With Flexible Hetero-Fabric Dataflow Orchestration and Compute/Storage-Density-Adjustable CIM

Li, Y., Gao, W., Jia, W., Lin, X., Yu, S., He, Y., Wang, W., Li, X., Zhang, L., Xie, Y., et al. (2026) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2026.3720642

Scalable and Programmable Neural Network Inference Accelerator Based on In-Memory Computing

Jia, H., Ozatay, M., Tang, Y., Valavi, H., Pathak, R., Lee, J., & Verma, N. (2021) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2021.3119018 · Cited by 122

PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference

Zhang, B., Yin, S., Kim, M., Saikia, J., Kwon, S., Myung, S., Kim, H., Kim, S. J., Seo, J.-S., & Seok, M. (2022) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2022.3211290 · Cited by 80

PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference

Yin, S., Zhang, B., Kim, M., Saikia, J., Kwon, S., Myung, S., Kim, H., Kim, S. J., Seok, M., & Seo, J.-S. (2021) · Symposium on VLSI Circuits · doi:10.23919/vlsicircuits52068.2021.9492403 · Cited by 40

A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing

Jia, H., Valavi, H., Tang, Y., Zhang, J., & Verma, N. (2020) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2020.2987714 · Cited by 233

A Microprocessor implemented in 65nm CMOS with Configurable and Bit-scalable Accelerator for Programmable In-memory ComputingPreprint

Jia, H., Tang, Y., Valavi, H., Zhang, J., & Verma, N. (2018) · arXiv (Cornell University) · doi:10.48550/arxiv.1811.04047 · Cited by 14