A Non-Idealities Aware Software–Hardware Co-Design Framework for Edge-AI Deep Neural Network Implemented on Memristive Crossbar
Abstract
In this work, a non-idealities aware software-hardware co-design framework for deep neural network (DNN) implemented on memristive crossbar is presented. The device level non-ideal factors such as device conductance variation, nonuniform quantization levels, device-to-device variation and programming failure probability are included in the model. At array level, the impact of line resistance and sneak path are considered using a new fast and accurate line resistance estimation model. The non-linearity and offset of the peripheral circuits are also considered. By incorporating these factors into a unified DNN training process, the neural network performance can be evaluated holistically. Furthermore, the proposed training process can effectively mitigate the impact of these non-idealities and reduce the inference accuracy degradations. Implemented in a hybrid fashion of Python and PyTorch, the proposed framework is evaluated with a simplified 5-layer VGG network implemented on measured$128\times 128$RRAM array with 3-level weight resolution. For CIFAR-10 tasks, 83% inference accuracy is achieved with less than 3% accuracy drop compared to the ideal model.
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The reduction in voltage is due to accumulated voltage drop on the connecting traces and sneak pathways.
“This reduction is due to the accumulated voltage drop on the connecting traces and sneak pathways [29].”
From Framework for In-Memory Computing Based on Memristor and Memcapacitor for On-Chip Training (2023) · cites this paper as [29]
Cites
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“To speed up the computation, the most time consuming VMM operations are implemented in NVIDA CUDA and processed in GPU.”
MethodEyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
Chen, Y.-H., Krishna, T., Emer, J. S., & Sze, V. (2017) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2016.2616357 · Cited by 3,247 · see citing works
Fully hardware-implemented memristor convolutional neural network
Yao, P., Wu, H., Gao, B., Tang, J., Zhang, Q., Zhang, W., Yang, J. J., & Qian, H. (2020) · Nature · doi:10.1038/s41586-020-1942-4 · Cited by 2,179 · cited 1× · see citing works
“Due to fabrication imperfectness, memristor crossbar exhibits various non-idealities, ranging from the device level conductance variation, device failure, programming failure [19], [20], [21] to the array level line resistance parasitics and sneak path [22].”
Background4K-memristor analog-grade passive crossbar circuit
Kim, H., Mahmoodi, M. R., Nili, H., & Strukov, D. B. (2021) · Nature Communications · doi:10.1038/s41467-021-25455-0 · Cited by 265 · see citing works
Sun, X., & Yu, S. (2019) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2019.2933148 · Cited by 170 · see citing works
A fully hardware-based memristive multilayer neural network
Kiani, F., Yin, J., Wang, Z., Yang, J. J., & Xia, Q. (2021) · Science Advances · doi:10.1126/sciadv.abj4801 · Cited by 97 · cited 1× · see citing works
“Recently, with the recent advancements in device fabrication and novel device write-verify techniques, multi-level analog memristor crossbar arrays with resolution up to 8-bit have been demonstrated [16], [17], [18].”
BackgroundMNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems
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Framework for In-Memory Computing Based on Memristor and Memcapacitor for On-Chip Training
Singh, A., & Lee, B.-G. (2023) · IEEE Access · doi:10.1109/access.2023.3324375 · Cited by 19 · see citing works
- Authors
- Cao, T., Liu, C., Wang, W., Zhang, T., Lee, H. K., Li, M. H., Song, W., Chen, Z. X., Zhuo, V. Y.-Q., Wang, N., Zhu, Y., Gao, Y., & Goh, W. L.
- Affiliations
- Agency for Science, Technology and Research (SG)
- Nanyang Technological University (SG)
- Institute of Microelectronics (IME), A*STAR, Singapore
- ORCID
- Venue
- IEEE Journal on Emerging and Selected Topics in Circuits and Systems
- Published
- 2022-12
- Volume
- 12
- Issue
- 4
- Pages
- 934-943
- ISSN
- 2156-3357 (ISSN-L)
- 2156-3365
- OpenAlex
- W4312081519
- Cited by
- 34
- References
- 7
- Citations by year
- 2026: 9 · 2025: 14 · 2024: 5 · 2023: 4 · 2022: 2
- FWCI
- 1.71
- Type
- journal article
- Language
- en
- Open access
- closed
- Licence
- Locations
- IEEE Journal on Emerging and Selected Topics in Circuits and Systems (publishedVersion)
- DR-NTU (Nanyang Technological University) (submittedVersion)
- Funders
- Agency for Science, Technology and Research (A*STAR), Singapore under the Nanosystems at the Edge Programme (A18A1b0055)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Ferroelectric and Negative Capacitance Devices
- Keywords
- hardware-software co-design, memristor crossbar, edge AI, deep neural network, device non-idealities, conductance variation, sneak paths, resistive random access memory, VGG, CIFAR-10
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