MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems
Abstract
Memristor based neuromorphic computing systems give alternative solutions to boost the computing energy efficiency of Neural Network (NN) algorithms. Because of the large-scale applications and the large architecture design space, many factors will affect the computing accuracy and system's performance. In this work, we propose a behavior-level modeling tool for memristor-based neuromorphic computing systems, MNSIM 2.0, to model the performance and help researchers to realize an early-stage design space exploration. Compared with the former version and other benchmarks, MNSIM 2.0 has the following new features: 1. In the algorithm level, MNSIM 2.0 supports the inference accuracy simulation for mixed-precision NNs considering non-ideal factors. 2. In the architecture level, a hierarchical modeling structure for PIM systems is proposed. Users can customize their designs from the aspects of devices, interfaces, processing units, buffer designs, and interconnections. 3. Two hardware-aware algorithm optimization methods are integrated in MNSIM 2.0 to realize software-hardware co-optimization.
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Existing modeling tools such as MNSIM have mainly emphasized evaluation of system area and power, potentially neglecting device variations and simplifying non-idealities calculations.
“Existing modeling tools such as MNSIM [15] have mainly emphasized the evaluation of system area and power, potentially neglecting device variations and simplifying non-idealities calculations.”
From Framework for In-Memory Computing Based on Memristor and Memcapacitor for On-Chip Training (2023) · cites this paper as [15]
Cites
Deep Residual Learning for Image Recognition
He, K., Zhang, X., Ren, S., & Sun, J. (2016) · 2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR) · doi:10.1109/cvpr.2016.90 · Cited by 235,474 · see citing works
Very Deep Convolutional Networks for Large-Scale Image Recognition
Simonyan, K., & Zisserman, A. (2014) · arXiv · doi:10.48550/arxiv.1409.1556 · Cited by 74,248 · see citing works
Gradient-based learning applied to document recognition
Lecun, Y., Bottou, L., Bengio, Y., & Haffner, P. (1998) · Proceedings of the IEEE · doi:10.1109/5.726791 · Cited by 58,805 · see citing works
Shafiee, A. R., Nag, A., Muralimanohar, N., Balasubramonian, R., Strachan, J. P., Hu, M., Williams, R. S., & Srikumar, V. (2016) · ACM SIGARCH Computer Architecture News · doi:10.1145/3007787.3001139 · Cited by 1,538 · see citing works
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory
Dong, X., Xu, C., Xie, Y., & Jouppi, N. P. (2012) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2012.2185930 · Cited by 1,234 · see citing works
Self-citationChi, P., Li, S., Xu, C., Zhang, T., Zhao, J., Liu, Y., Wang, Y., & Xie, Y. (2016) · ACM SIGARCH Computer Architecture News · doi:10.1145/3007787.3001140 · Cited by 1,226 · see citing works
Self-citationCACTI: an enhanced cache access and cycle time model
Wilton, S. J. E., & Jouppi, N. P. (1996) · IEEE Journal of Solid-State Circuits · doi:10.1109/4.509850 · Cited by 872 · see citing works
ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars
Shafiee, A., Nag, A., Muralimanohar, N., Balasubramonian, R., Strachan, J. P., Hu, M., Williams, R. S., & Srikumar, V. (2016) · 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA) · doi:10.1109/isca.2016.12 · Cited by 775 · see citing works
Peng, X., Huang, S., Luo, Y., Sun, X., & Yu, S. (2019) · Technical digest - International Electron Devices Meeting/Technical digest · doi:10.1109/iedm19573.2019.8993491 · Cited by 366 · see citing works
MNSIM: Simulation Platform for Memristor-based Neuromorphic Computing System
Xia, L., Li, B., Tang, T., Gu, P., Chen, P.-Y., Yu, S., Cao, Y. K., Wang, Y., Xie, Y., & Yang, H. (2017) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2017.2729466 · Cited by 186 · see citing works
Self-citationNVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Non-volatile Memory
Dong, X., Xu, C., Jouppi, N. P., & Xie, Y. (2013) · Springer eBooks · doi:10.1007/978-1-4419-9551-3_2 · Cited by 176 · see citing works
Self-citationA Configurable Multi-Precision CNN Computing Framework Based on Single Bit RRAM
Zhu, Z., Sun, H., Lin, Y., Dai, G., Xia, L., Han, S., Wang, Y., & Yang, H. (2019) · ACM/IEEE Design Automation Conference (DAC) · doi:10.1145/3316781.3317739 · Cited by 101 · see citing works
Self-citationKull, L., Luu, D., Menolfi, C., Brändli, M., Francese, P. A., Morf, T., Kossel, M., Yueksel, H., Cevrero, A., Özkaya, İ., et al. (2017) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.2017.7870467 · Cited by 97 · see citing works
27.3 Area-efficient 1GS/s 6b SAR ADC with charge-injection-cell-based DAC
Choo, K. D., Bell, J., & Flynn, M. P. (2016) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · doi:10.1109/isscc.2016.7418106 · Cited by 80 · see citing works
Design Guidelines of RRAM based Neural-Processing-Unit
Zhang, W., Peng, X., Wu, H., Gao, B., He, H., Zhang, Y., Yu, S., & Qian, H. (2019) · ACM/IEEE Design Automation Conference (DAC) · doi:10.1145/3316781.3317797 · Cited by 54 · see citing works
Sun, H., Zhu, Z., Cai, Y., Chen, X., Wang, Y., & Yang, H. (2020) · Asia and South Pacific Design Automation Conference (ASP-DAC) · doi:10.1109/asp-dac47756.2020.9045192 · Cited by 41 · see citing works
Self-citationInterconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs
Krishnan, G., V, Mandal, S. K., Chakrabarti, C., Seo, J.-S., Ogras, U. Y., & Cao, Y. K. (2020) · IEEE Design and Test · doi:10.1109/mdat.2020.3001559 · Cited by 37 · see citing works
Self-citationSuppress variations of analog resistive memory for neuromorphic computing by localizing Vo formation
Wu, W., Wu, H.-Q., Gao, B., Deng, N., & Qian, H. (2018) · Journal of Applied Physics · doi:10.1063/1.5037896 · Cited by 25 · see citing works
Analytical Performance Models for NoCs with Multiple Priority Traffic Classes
Mandal, S. K., Ayoub, R. Z., Kishinevsky, M., & Ogras, U. Y. (2019) · ACM Transactions on Embedded Computing Systems · doi:10.1145/3358176 · Cited by 25 · see citing works
A 700 μW 1GS/s 4-bit folding-flash ADC in 65nm CMOS for wideband wireless communications
Nasri, B., Sebastian, S. P., You, K.-D., RanjithKumar, R., & Shahrjerdi, D. (2017) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.2017.8050624 · Cited by 20 · see citing works
A >3GHz ERBW 1.1GS/S 8B Two-Sten SAR ADC with Recursive-Weight DAC
Chen, H., Zhot, X., Yu, Q., Zhang, F., & Li, Q. (2018) · Symposium on VLSI Circuits · doi:10.1109/vlsic.2018.8502370 · Cited by 20 · see citing works
Automatic endosomal structure detection and localization in fluorescence microscopic images
Lin, D., Lin, Z., Velmurugan, R., & Ober, R. J. (2017) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.2017.8050242 · Cited by 4 · see citing works
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Aguirre, F., Sebastian, A., Le Gallo, M., Song, W., Wang, T., Yang, J. J., Lu, W., Chang, M.-F., Ielmini, D., Yang, Y., et al. (2024) · Nature Communications · doi:10.1038/s41467-024-45670-9 · Cited by 499 · see citing works
“MNSIM 240,241 , proposes a hierarchical structure for memristor-based neuromorphic computing accelerators, with interfaces for customization.”
A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators, and Security
Staudigl, F., Merchant, F., & Leupers, R. (2021) · IEEE Design and Test · doi:10.1109/mdat.2021.3102013 · Cited by 75 · see citing works
SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks
Krishnan, G., Mandal, S. K., Pannala, M., Chakrabarti, C., Seo, J.-S., Ogras, U. Y., & Cao, Y. (2021) · ACM Transactions on Embedded Computing Systems · doi:10.1145/3476999 · Cited by 67 · see citing works
Self-citationTxSim: Modeling Training of Deep Neural Networks on Resistive Crossbar Systems
Roy, S., Sridharan, S., Jain, S., & Raghunathan, A. (2021) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2021.3063543 · Cited by 52 · see citing works
Cao, T., Liu, C., Wang, W., Zhang, T., Lee, H. K., Li, M. H., Song, W., Chen, Z. X., Zhuo, V. Y.-Q., Wang, N., et al. (2022) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2022.3214334 · Cited by 34 · see citing works
Neural architecture search for in-memory computing-based deep learning accelerators
Krestinskaya, O., Fouda, M. E., Benmeziane, H., Maghraoui, K. E., Sebastian, A., Lu, W. D., Lanza, M., Li, H. H., Kurdahi, F. J., Fahmy, S. A., et al. (2024) · Nature Reviews Electrical Engineering · doi:10.1038/s44287-024-00052-7 · Cited by 35 · see citing works
A Survey of Computing-in-Memory Processor: From Circuit to Application
Sun, W., Yue, J., He, Y., Huang, Z., Wang, J., Jia, W., Li, Y., Lei, L., Jia, H., & Liu, Y. (2023) · IEEE Open Journal of the Solid-State Circuits Society · doi:10.1109/ojsscs.2023.3328290 · Cited by 32 · see citing works
Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks
Krishnan, G., V, Mandal, S. K., Chakrabarti, C., Seo, J.-S., Ogras, U. Y., & Cao, Y. K. (2021) · ACM Journal on Emerging Technologies in Computing Systems · doi:10.1145/3460233 · Cited by 27 · see citing works
Self-citationLayer ensemble averaging for fault tolerance in memristive neural networks
Yousuf, O., Hoskins, B. D., Ramu, K., Fream, M., Borders, W. A., Madhavan, A., Daniels, M. W., Dienstfrey, A., McClelland, J. J., Lueker-Boden, M., et al. (2025) · Nature Communications · doi:10.1038/s41467-025-56319-6 · Cited by 22 · see citing works
Framework for In-Memory Computing Based on Memristor and Memcapacitor for On-Chip Training
Singh, A., & Lee, B.-G. (2023) · IEEE Access · doi:10.1109/access.2023.3324375 · Cited by 19 · see citing works
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Sun, X., Wang, X., Li, W., Wang, L., Han, Y., & Chen, X. (2023) · ACM/IEEE Design Automation Conference (DAC) · doi:10.1109/dac56929.2023.10247928 · Cited by 21 · see citing works
Self-citationLiu, Y., Gao, B., Tang, J., Wu, H., & Qian, H. (2023) · Science China Information Sciences · doi:10.1007/s11432-023-3785-8 · Cited by 20 · see citing works
Wu, X., Hanson, E., Wang, N., Zheng, Q., Yang, X., Yang, H., Li, S., Cheng, F., Pande, P. P., Doppa, J. R., et al. (2024) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2024.3409193 · Cited by 16 · see citing works
Self-citationExploring Model Stability of Deep Neural Networks for Reliable RRAM-Based In-Memory Acceleration
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Self-citationGibbon: Efficient Co-Exploration of NN Model and Processing-In-Memory Architecture
Sun, H., Wang, C., Zhu, Z., Ning, X., Dai, G., Yang, H., & Wang, Y. (2022) · 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) · doi:10.23919/date54114.2022.9774605 · Cited by 15 · see citing works
Self-citationLiu, Y., Zhao, M., Gao, B., Hu, R., Zhang, W., Yang, S., Yao, P., Xu, F., Xi, Y., Zhang, Q., et al. (2021) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2021.3069746 · Cited by 15 · see citing works
Gibbon: An Efficient Co-Exploration Framework of NN Model and Processing-In-Memory Architecture
Sun, H., Zhu, Z., Wang, C., Ning, X., Dai, G., Yang, H., & Wang, Y. (2023) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2023.3262201 · Cited by 13 · see citing works
Self-citationEnhancing Security of Memristor Computing System Through Secure Weight Mapping
Zou, M., Zhou, J., Cui, X., Wang, W. J., & Kvatinsky, S. (2022) · IEEE Computer Society Annual Symposium on VLSI · doi:10.1109/isvlsi54635.2022.00044 · Cited by 12 · see citing works
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Chiang, H.-W., Nien, C.-F., Cheng, H.-Y., & Huang, K.-P. (2024) · Proceedings - International Symposium on Computer Architecture/Proceedings · doi:10.1109/isca59077.2024.00015 · Cited by 10 · see citing works
Wu, B., Liu, Y., Liu, J., Huan, C., Wei, X., Tong, W., & Feng, D. (2024) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2024.3485589 · Cited by 9 · see citing works
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Zou, M., Du, N., & Kvatinsky, S. (2022) · Frontiers in Electronic Materials · doi:10.3389/femat.2022.1010613 · Cited by 9 · see citing works
Zhu, Y. M., Zhu, Z., Dai, G., Tu, F., Sun, H., Cheng, K.-T. T., Yang, H., & Wang, Y. (2023) · ACM/IEEE Design Automation Conference (DAC) · doi:10.1109/dac56929.2023.10247755 · Cited by 9 · see citing works
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Qian, Y., Zhao, L., Meng, F., Xu, X., Zhuo, C., & Yin, X. (2024) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2024.3409648 · Cited by 6 · see citing works
Rahmani, A. M., Naqvi, R. A., Ali, S., Mirmahaleh, S. Y. H., Alswaitti, M., Hosseinzadeh, M., & Siddique, K. (2021) · Mathematics · doi:10.3390/math9233012 · Cited by 6 · see citing works
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Wang, X., Sun, X., Han, Y., & Chen, X. (2024) · Design, Automation, and Test in Europe · doi:10.23919/date58400.2024.10546788 · Cited by 4 · see citing works
Self-citationA flexible and fast digital twin for RRAM systems applied for training resilient neural networks
Fritscher, M., Singh, S., Rizzi, T., Baroni, A., Reiser, D., Mallah, M., Hartmann, D., Bende, A., Kempen, T., Uhlmann, M., et al. (2024) · Scientific Reports · doi:10.1038/s41598-024-73439-z · Cited by 4 · see citing works
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Jiang, Y., Gao, B., Tang, J., Wu, D., He, H., Qian, H., & Wu, H. (2021) · IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) · doi:10.1109/icta53157.2021.9661827 · Cited by 4 · see citing works
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Wang, Z., Yue, J., He, C., Dai, Z., Xiang, F., Cong, Z., He, Y., Feng, X., & Liu, Y. (2023) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas46773.2023.10182131 · Cited by 3 · see citing works
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Zhang, T., Cheng, D., He, Y., Chen, Z., Dai, X., Xiong, L., Liu, Y., Cheng, F., Cao, Y., Yan, F., et al. (2024) · ACM Transactions on Recommender Systems · doi:10.1145/3706124 · Cited by 2 · see citing works
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Ahsan, S. M. M., Shahriar, M. S., Chowdhury, M., Hossain, T., Hasan, M. S., & Hoque, T. (2024) · doi:10.1145/3676536.3676827 · Cited by 2 · see citing works
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EPIM: Efficient Processing-In-Memory Accelerators based on Epitome
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Tripathy, R., & Mandal, S. K. (2025) · IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) · doi:10.1109/ispass64960.2025.00058 · Cited by 1 · see citing works
Reliability-Aware Training and Performance Modeling for Processing-In-Memory Systems
Sun, H., Zhu, Z., Cai, Y., Zeng, S., Qiu, K., Wang, Y., & Yang, H. (2021) · Asia and South Pacific Design Automation Conference (ASP-DAC) · doi:10.1145/3394885.3431633 · Cited by 1 · see citing works
Self-citationBenQ: Benchmarking Automated Quantization on Deep Neural Network Accelerators
Wei, Z., Zhang, X., Li, J., Ji, Z., & Wei, J. (2022) · Design, Automation, and Test in Europe · doi:10.23919/date54114.2022.9774652 · Cited by 1 · see citing works
Vadivel, K., Garćıa-Redondo, F., BanaGozar, A., Corporaal, H., & Das, S. (2022) · Conference on Design of Circuits and Integrated Systems · doi:10.1109/dcis55711.2022.9970090 · Cited by 1 · see citing works
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Park, J., Kim, B. J., & Sung, H. (2024) · International Conference on Parallel Architectures and Compilation Techniques (PACT) · doi:10.1145/3656019.3676946
Heo, D., Bang, H., & Ko, J. H. (2024) · ACM/IEEE Design Automation Conference (DAC) · doi:10.1145/3649329.3656535
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Liu, T.-Y., Lu, Y.-A., Yu, J., Nien, C.-F., & Cheng, H.-Y. (2025) · Asia and South Pacific Design Automation Conference (ASP-DAC) · doi:10.1145/3658617.3697571
Vungarala, D., Amin, M. H., Roohi, A., Ghosh, A., Zand, R., & Angizi, S. (2025) · ACM Great Lakes Symposium on VLSI (GLSVLSI) · doi:10.1145/3716368.3735276
Wang, L., Jiang, P., Zhang, Z., Yang, Y., Fang, Y., Wang, Y., Zhu, M., Miao, X., & Wang, X. (2025) · IEEE Electron Devices Technology & Manufacturing Conference (EDTM) · doi:10.1109/edtm61175.2025.11040746
Self-citationASMA: An Anisotropy Scaling Memristor-Based Accelerator for LLM Inference
Xiong, Z., Yang, X., Zhang, Y., Zhou, Y., Yang, J., Tao, Y., Miao, X., & He, Y. (2025) · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · doi:10.1109/iccd65941.2025.00086
Staudigl, F., & Leupers, R. (2026) · Synthesis lectures on engineering, science, and technology · doi:10.1007/978-3-032-09586-2_3
Securing RRAM-Based Neural Networks Via Neuron-Level Activation-Triggered Perturbation
Zhao, X., Chen, X., Zhang, S., Sun, J., Wang, J., & Chen, S. (2026) · Journal of Circuits Systems and Computers · doi:10.1142/s021812662650194x
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Wu, T., He, S., Chen, W., Zhang, X., & Shi, T. (2026) · IEEE Transactions on Computers · doi:10.1109/tc.2026.3727031
- Authors
- Zhu, Z., Sun, H., Qiu, K., Xia, L., Krishnan, G., Dai, G., Niu, D., Chen, X., Hu, X. S., Cao, Y., Xie, Y., Wang, Y., & Yang, H.
- Affiliations
- Tsinghua University (CN)
- Alibaba Group (China) (CN)
- Arizona State University, Phoenix, AZ, USA
- Alibaba Group, Sunnyvale, CA, USA
- Chinese Academy of Sciences (CN)
- University of Notre Dame (US)
- Arizona State University (US)
- University of California, Santa Barbara (US)
- ORCID
- Venue
- Proceedings of the 2020 on Great Lakes Symposium on VLSI
- Publisher
- ACM
- Published
- 2020-09-07
- Pages
- 83-88
- OpenAlex
- W3083443371
- Cited by
- 77
- References
- 22
- Citations by year
- 2026: 4 · 2025: 9 · 2024: 22 · 2023: 23 · 2022: 8 · 2021: 11
- FWCI
- 14.77
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- ACM Great Lakes Symposium on VLSI (GLSVLSI) (publishedVersion)
- Rare & Special e-Zone (The Hong Kong University of Science and Technology) (submittedVersion)
- Funders
- National Natural Science Foundation of China (61832007, 61622403, 61621091, U19B2019)
- Beijing Academy of Artificial Intelligence under Grant (BAAI2019QN0402)
- National Key Research and Development Program of China (2017YFA0207600)
- Beijing National Research Center for Information Science and Technology (BNRist)
- Beijing Innovation Center for Future Chips
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Life Sciences › Biochemistry, Genetics and Molecular Biology › Molecular Biology › DNA and Biological Computing
- Keywords
- design space exploration, in-memory computing, hierarchical models, hardware-software co-design, energy efficiency
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Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
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