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Bridging the Processor-Memory Performance Gapwith 3D IC Technology
Abstract
Microprocessor performance has been improving at roughly 60% per year. Memory access times, however, have improved by less than 10% per year. The resulting gap between logic and memory performance has forced microprocessor designs toward complex and power-hungry architectures that support out-of-order and speculative execution. Moreover, processors have been designed with increasingly large cache hierarchies to hide main memory latency. This article examines how 3D IC technology can improve interactions between the processor and memory. Our work examines the performance of a single-core, single-threaded processor under representative work loads. We have shown that reducing memory latency by bringing main memory on chip gives us near-perfect performance. Three-dimensional IC technology can provide the much needed bandwidth without the cost, design complexity, and power issues associated with a large number of off-chip pins. The principal challenge remains the demonstration of a highly manufacturable 3D IC technology with high yield and low cost.
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Cited by
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology
Kang, U., Chung, H.-J., Heo, S., Park, D.-H., Lee, H., Kim, J. H., Ahn, S.-H., Cha, S.-H., Ahn, J., Kwon, D., et al. (2010) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2009.2034408 · Cited by 485
3D-Stacked Memory Architectures for Multi-core Processors
Loh, G. H. (2008) · 2008 International Symposium on Computer Architecture · doi:10.1109/isca.2008.15 · Cited by 438
Data-Centric Computing Frontiers: A Survey On Processing-In-Memory
Siegl, P., Buchty, R., & Berekovic, M. (2016) · Proceedings of the Second International Symposium on Memory Systems · doi:10.1145/2989081.2989087 · Cited by 55
3D DRAM Design and Application to 3D Multicore Systems
Sun, H., Liu, J., Anigundi, R. S., Zheng, N., Lu, J.-Q., Rose, K., & Zhang, T. (2009) · IEEE Design & Test of Computers · doi:10.1109/mdt.2009.105 · Cited by 53
Metadata
- Authors
- Liu, C. C., Ganusov, I., Burtscher, M., & Tiwari, S.
- Venue
- IEEE Design and Test of Computers
- Published
- 2005-06
- Volume
- 22
- Issue
- 6
- Pages
- 556-564
- ISSN
- 0740-7475 (ISSN-L)
- OpenAlex
- W2122636510
- Cited by
- 280
- References
- 0
- FWCI
- 11.12
- Type
- journal article
- Language
- en
- Open access
- closed
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- Liu, C. C., Ganusov, I., Burtscher, M., & Tiwari, S. (2005). Bridging the Processor-Memory Performance Gapwith 3D IC Technology. IEEE Design and Test of Computers. https://doi.org/10.1109/mdt.2005.134
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