The DOI matches its Crossref record; 7 of the 7 references it cites were found in a registry or an index.
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning
Abstract
Neuro-inspired architectures based on synaptic memory arrays have been proposed for on-chip acceleration of weighted sum and weight update in machine/deep learning algorithms. In this paper, we developed NeuroSim, a circuit-level macro model that estimates the area, latency, dynamic energy, and leakage power to facilitate the design space exploration of neuro-inspired architectures with mainstream and emerging device technologies. NeuroSim provides flexible interface and a wide variety of design options at the circuit and device level. Therefore, NeuroSim can be used by neural networks (NNs) as a supporting tool to provide circuit-level performance evaluation. With NeuroSim, an integrated framework can be built with hierarchical organization from the device level (synaptic device properties) to the circuit level (array architectures) and then to the algorithm level (NN topology), enabling instruction-accurate evaluation on the learning accuracy as well as the circuit-level performance metrics at the run-time of online learning. Using multilayer perceptron as a case-study algorithm, we investigated the impact of the “analog” emerging nonvolatile memory (eNVM)'s “nonideal” device properties and benchmarked the tradeoffs between SRAM, digital, and analog eNVM-based architectures for online learning and offline classification.
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Cites
Gradient-based learning applied to document recognition
Lecun, Y., Bottou, L., Bengio, Y., & Haffner, P. (1998) · Proceedings of the IEEE · doi:10.1109/5.726791 · Cited by 58,805
Nanoscale Memristor Device as Synapse in Neuromorphic Systems
Jo, S. H., Chang, T., Ebong, I., Bhadviya, B. B., Mazumder, P., & Lu, W. (2010) · Nano Letters · doi:10.1021/nl904092h · Cited by 4,174 · cited 3×
“For example, Ag:a-Si devices [20] show a nonlinear and noisy weight increase/decrease; though TaOx/TiO2 devices [21] exhibit a more linear and smooth weight increase/decrease, the ON/OFF ratio is very limited (∼2).”
BackgroundMethodTraining and operation of an integrated neuromorphic network based on metal-oxide memristors
Prezioso, M., Merrikh-Bayat, F., Hoskins, B. D., Adam, G. C., Likharev, K. K., & Strukov, D. B. (2015) · Nature · doi:10.1038/nature14441 · Cited by 3,001
Nanoelectronic programmable synapses based on phase change materials for brain-inspired computing
Kuzum, D., Jeyasingh, R. G. D., Lee, B., & Wong, H.-S. P. (2012) · Nano Letters · doi:10.1021/nl201040y · Cited by 1,267 · cited 1×
“To achieve even higher integration density, faster speed, and lower programming voltage, compact synaptic devices based on eNVM are proposed for the neuromorphic systems, including resistive random access memory [20]–[25] and phase change memory [11], [26], [27], etc.”
MethodBurr, G. W., Shelby, R. M., Sidler, S., di Nolfo, C., Jang, J., Boybat, I., Shenoy, R. S., Narayanan, P., Virwani, K., Giacometti, E. U., et al. (2015) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2015.2439635 · Cited by 936
Woo, J., Moon, K., Song, J., Lee, S., Kwak, M., Park, J., & Hwang, H. (2016) · IEEE Electron Device Letters · doi:10.1109/led.2016.2582859 · Cited by 512 · cited 1×
“Such nonideal behaviors commonly exist in today’s synaptic devices [20]–[23], possibly due to the inherent drift and diffusion dynamics of the ions/vacancies in these materials.”
BackgroundSuri, M., Bichler, O., Querlioz, D., Cueto, O., Perniola, L., Sousa, V., Vuillaume, D., Gamrat, C., & DeSalvo, B. (2011) · 2011 International Electron Devices Meeting · doi:10.1109/iedm.2011.6131488 · Cited by 314
Cited by
Neuro-inspired computing chips
Zhang, W., Gao, B., Tang, J., Yao, P., Yu, S., Chang, M.-F., Yoo, H.-J., Qian, H., & Wu, H. (2020) · Nature Electronics · doi:10.1038/s41928-020-0435-7 · Cited by 892
Self-citationA fully integrated reprogrammable memristor–CMOS system for efficient multiply–accumulate operations
Cai, F., Correll, J. M., Lee, S. H., Lim, Y., Bothra, V., Zhang, Z., Flynn, M. P., & Lu, W. D. (2019) · Nature Electronics · doi:10.1038/s41928-019-0270-x · Cited by 728
Ferroelectric Analog Synaptic Transistors
Kim, M.-K., & Lee, J.-S. (2019) · Nano Letters · doi:10.1021/acs.nanolett.9b00180 · Cited by 594
Hardware implementation of memristor-based artificial neural networks
Aguirre, F., Sebastian, A., Le Gallo, M., Song, W., Wang, T., Yang, J. J., Lu, W., Chang, M.-F., Ielmini, D., Yang, Y., et al. (2024) · Nature Communications · doi:10.1038/s41467-024-45670-9 · Cited by 564
“For benchmarking a device or a chip, it is essential to evaluate the accuracy of standard deep neural network models like VGG 89 and ResNet 90 on CIFAR and ImageNet dataset by utilizing architecture-levelsimulationandrealistichardwarestatistics 91,92 .”
Peng, X., Huang, S., Jiang, H., Lu, A., & Yu, S. (2021) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2020.3043731 · Cited by 317
Self-citation
Metadata
- Authors
- Chen, P.-Y., Peng, X., & Yu, S.
- Venue
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Published
- 2018-12
- Volume
- 37
- Issue
- 12
- Pages
- 3067-3080
- ISSN
- 0278-0070 (ISSN-L)
- 1937-4151
- OpenAlex
- W2782046614
- Cited by
- 652
- References
- 7
- FWCI
- 14.58
- Type
- journal article
- Language
- en
- Open access
- closed
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- Chen, P.-Y., Peng, X., & Yu, S. (2018). NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. https://doi.org/10.1109/tcad.2018.2789723
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