An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS
Abstract
We present a robust, all-digital True Random Number Generator (TRNG) architecture that efficiently combines low-quality physical random number generators (PRNGs) with integrated de-correlation and de-biasing. A 65-nm CMOS TRNG test chip demonstrates NIST test-suite compliance across 0.5-1.0 V supply voltage $(V_{\text{dd}})$ and −20-100 °C, even with significant PRNG entropy $(H)$ degradation. The measured 2.58 pJ/bit is the lowest among all-digital NIST-compliant TRNGs. In terms of energy, area and performance metrics, this digital implementation is especially suited for advanced CMOS process nodes.
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Si-CMOS-based tRNGs use circuitry with various types of entropy sources, such as timing jitter, chaotic maps, metastability, or noise jitter from SRAM bit-line leakages, for low power consumption.
“In contrast, Si-CMOS–based tRNGs use circuitry that uses various types of entropy sources, such as timing jitter, chaotic maps, metastability, or noise jitter from SRAM bit-line leakages for low power consumption.”
From Cryptographic transistor for true random number generator with low power consumption (2024) · cites this paper as [21]
Si-CMOS-based tRNGs show excellent randomness and insensitivity to fabrication-induced variability.
“They show excellent randomness and insensitivity to fabrication-induced variability.”
From Cryptographic transistor for true random number generator with low power consumption (2024) · cites this paper as [21]
Those entropy sources rely on operation-induced variations.
“Note that those entropy sources rely on operation-induced variations (19–23).”
From Cryptographic transistor for true random number generator with low power consumption (2024) · cites this paper as [21]
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Iterating Von Neumann's Procedure for Extracting Random Bits
Peres, Y. (1992) · The Annals of Statistics · doi:10.1214/aos/1176348543 · Cited by 186 · see citing works
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Satpathy, S. K., Mathew, S. K., Kumar, R., Suresh, V., Anders, M. A., Kaul, H., Agarwal, A., Hsu, S., Krishnamurthy, R. K., & De, V. (2019) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2018.2886350 · Cited by 114 · see citing works
Taneja, S., Rajanna, V. K., & Alioto, M. (2021) · 2021 IEEE International Solid-State Circuits Conference (ISSCC) · doi:10.1109/isscc42613.2021.9366019 · Cited by 58 · see citing works
Cryptographic transistor for true random number generator with low power consumption
Kim, S.-I., You, H.-J., Kim, M.-S., An, U.-S., Kim, M.-S., Lee, D. H., Ryu, S.-T., & Choi, Y.-K. (2024) · Science Advances · doi:10.1126/sciadv.adk6042 · Cited by 33 · see citing works
Self-citation
- Authors
- Pamula, V. R., Sun, X., Kim, S., Rahman, F. U., Zhang, B., & Sathe, V. S.
- Affiliations
- University of Washington (US)
- Venue
- 2018 IEEE Symposium on VLSI Circuits
- Publisher
- IEEE
- Published
- 2018-06
- Pages
- 1-2
- ISSN
- 2166-9600 (ISSN-L)
- OpenAlex
- W2898748682
- Cited by
- 36
- References
- 3
- Citations by year
- 2026: 2 · 2025: 2 · 2024: 7 · 2023: 5 · 2022: 3 · 2021: 6 · 2020: 6 · 2019: 4 · 2018: 1
- FWCI
- 3.66
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- Symposium on VLSI Circuits (publishedVersion)
- Topics
- Physical Sciences › Computer Science › Hardware and Architecture › Physical Unclonable Functions (PUFs) and Hardware Security
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
- Keywords
- true random number generator, physical random number generators, bias correction, energy efficiency, 65 nm CMOS, low-voltage operation, low-temperature operation
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