A low-power and high-speed True Random Number Generator using generated RTN
Open accessAbstract
A novel True Random Number Generator (TRNG), using random telegraph noise (RTN) as the entropy source, is proposed to address speed, design area, power and cost simultaneously. For the first time, the proposed design breaks the inherent speed limitation and generates true random numbers up to 3Mbps with ultra-low power. This is over 10 times faster than the state-of-the-art RTN-TRNG [6]. Moreover, the new design does not require selection of devices and thus avoids the use of large transistor array and laborious post-selection process. This reduces the circuit area and the cost. The proposed TRNG has been successfully validated on three different processes and they all passed the National Institute of Standards and Technology (NIST) tests, making it a suitable candidate for future cryptographically secured applications in the internet of things (IoT).
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A MOSFET-based tRNG with 100% CMOS compatibility has been demonstrated for high scalability and applicability to an advanced foundry platform by using random telegraph noise or random charge trapping effects as an entropy source.
“As an alternative to the circuit-based tRNGs, a MOSFET-based tRNG with 100% CMOS compatibility has been demonstrated for high scalability and applicability to an advanced foundry platform by using random telegraph noise or random charge trapping effects as an entropy source (24–26).”
From Cryptographic transistor for true random number generator with low power consumption (2024) · cites this paper as [24]
The Abstract and RTN generation and characterization section describe an nFET-based generator that uses stress-generated random telegraph noise, avoids a large transistor array, and was validated on three processes. Table II includes a 22 nm FinFET process, but our copy does not establish the claimed 100% CMOS compatibility or identify the processes as advanced foundry platforms. Page numbers are not available in our copy. (LLM, conf=0.84)
Experimental — accuracy not yet measuredThe MOSFET-based tRNG's randomness is not fully verified, and high power consumption remains a problem in some cases.
“However, its randomness is not fully verified, and high power consumption remains a problem in some cases.”
From Cryptographic transistor for true random number generator with low power consumption (2024) · cites this paper as [24]
The Introduction (Abstract section) says TRNG power consumption is often high, supporting the qualified power concern for TRNGs generally. But the paper says its proposed transistor-based design passed NIST tests across three processes and describes it as ultra-low-power (Abstract; Conclusions). It therefore does not support the claim that this design’s randomness was not fully verified. (LLM, conf=0.86)
Experimental — accuracy not yet measured
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Cites
Bucci, M., Germani, L., Luzzi, R., Trifiletti, A., & Varanonuovo, M. (2003) · IEEE Transactions on Computers · doi:10.1109/tc.2003.1190581 · Cited by 403 · see citing works
Lu, C.-C., Chang‐Liao, K., Tsao, C.-H., et al. (2014) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2014.2303885 · Cited by 8 · see citing works
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Research works printed but not linked: 1
- M. Bucci et al, p. 403, IEEE Trans. Comput 2003.
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Cryptographic transistor for true random number generator with low power consumption
Kim, S.-I., You, H.-J., Kim, M.-S., An, U.-S., Kim, M.-S., Lee, D. H., Ryu, S.-T., & Choi, Y.-K. (2024) · Science Advances · doi:10.1126/sciadv.adk6042 · Cited by 33 · see citing works
“As an alternative to the circuit-based tRNGs, a MOSFET-based tRNG with 100% CMOS compatibility has been demonstrated for high scalability and applicability to an advanced foundry platform by using random telegraph noise or random charge trapping effects as an entropy source ( 24 – 26 ).”
Xiao, Y., Hsieh, E. R., Chung, S. S., Chen, T. R., Huang, S. A., Chen, T. J., & Cheng, O. (2019) · 2019 IEEE International Electron Devices Meeting (IEDM) · doi:10.1109/iedm19573.2019.8993496 · Cited by 11 · see citing works
- Authors
- Brown, J., Gao, R., Ji, Z., Chen, J., Wu, J., Zhang, J., Zhou, B., Shi, Q., Crowford, J., & Zhang, W.
- Affiliations
- Liverpool John Moores University (GB)
- Shandong University (CN)
- ORCID
- Venue
- 2018 IEEE Symposium on VLSI Technology
- Publisher
- IEEE
- Published
- 2018-06
- Pages
- 95-96
- OpenAlex
- W2899391577
- Cited by
- 39
- References
- 2
- Citations by year
- 2026: 3 · 2024: 6 · 2023: 2 · 2022: 8 · 2021: 6 · 2020: 7 · 2019: 7
- FWCI
- 4.30
- Type
- conference paper
- Language
- en
- Open access
- Locations
- Symposium on VLSI Technology (publishedVersion)
- Liverpool John Moores University (submittedVersion)
- Topics
- Physical Sciences › Computer Science › Hardware and Architecture › Physical Unclonable Functions (PUFs) and Hardware Security
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
- Keywords
- true random number generator, random telegraph noise, entropy source, low power design, high-speed random number generation, NIST randomness tests, Internet of Things security
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