A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays

An analog-AI chip for energy-efficient speech recognition and transcription

Ambrogio, S., Narayanan, P., Okazaki, A., Fasoli, A., Mackin, C., Hosokawa, K., Nomura, A., Yasuda, T., Chen, A., Friz, A., et al. (2023) · Nature · doi:10.1038/s41586-023-06337-5 · Cited by 269

Programming memristor arrays with arbitrarily high precision for analog computing

Song, W., Rao, M., Li, Y., Li, C., Zhuo, Y., Cai, F., Wu, M.-C., Yin, W., Zongze, L., Wei, Q., et al. (2024) · Science · doi:10.1126/science.adi9405 · Cited by 217

A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference

Ye, W., Wang, L., Zhou, Z., An, J., Li, W., Gao, H., Li, Z., Yue, J., Hu, H., Xu, X., et al. (2023) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2023.3280357 · Cited by 66

Advances of embedded resistive random access memory in industrial manufacturing and its potential applications

Wang, Z., Song, Y., Zhang, G., Luo, Q., Xu, K., Gao, D., Yu, B., Loke, D. K., Zhong, S., & Zhang, Y. (2024) · International Journal of Extreme Manufacturing · doi:10.1088/2631-7990/ad2fea · Cited by 49

In-Memory Computing for Machine Learning and Deep Learning

Lepri, N., Glukhov, A., Cattaneo, L., Farronato, M., Mannocci, P., & Ielmini, D. (2023) · IEEE Journal of the Electron Devices Society · doi:10.1109/jeds.2023.3265875 · Cited by 52

Nonvolatile Capacitive Synapse: Device Candidates for Charge Domain Compute-In-Memory

Yu, S., Luo, Y.-C., Kim, T., & Phadke, O. (2023) · IEEE Electron Devices Magazine · doi:10.1109/med.2023.3293060 · Cited by 43

Roadmap on low-power electronics

Ramesh, R., Salahuddin, S., Datta, S., Diaz, C. H., Nikonov, D. E., Young, I. A., Ham, D., Chang, M., Khwa, W.-S., Lele, A. S., et al. (2024) · APL Materials · doi:10.1063/5.0184774 · Cited by 43

An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree

He, Y., Yue, J., Feng, X., Huang, Y., Jia, H., Wang, J., Zhang, L., Sun, W., Yang, H., & Liu, Y. (2022) · IEEE Transactions on Circuits & Systems II Express Briefs · doi:10.1109/tcsii.2022.3209872 · Cited by 36

ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays

Jiang, H., Huang, S., Li, W., & Yu, S. (2022) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2022.3208755 · Cited by 35

H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention

Li, W., Manley, M., Read, J., Kaul, A., Bakir, M. S., & Yu, S. (2023) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2023.3299509 · Cited by 34

Resistive Neural Hardware Accelerators

Smagulova, K., Fouda, M., Kurdahi, F., Salama, K., & Eltawil, A. (2021) · Proceedings of the IEEE · doi:10.1109/jproc.2023.3268092 · Cited by 30

Efficient nonlinear function approximation in analog resistive crossbars for recurrent neural networks

Yang, J., Mao, R., Jiang, M., Cheng, Y., Sun, P.-S. V., Dong, S., Pedretti, G., Sheng, X., Ignowski, J., Li, H., et al. (2025) · Nature Communications · doi:10.1038/s41467-025-56254-6 · Cited by 28

A 22 nm Floating-Point ReRAM Compute-in-Memory Macro Using Residue-Shared ADC for AI Edge Device

Hsu, H.-H., Wen, T.-H., Khwa, W.-S., Huang, W.-H., Ke, Z.-E., Chin, Y.-H., Wen, H.-J., Chang, Y., Hsu, W., Lele, A. S., et al. (2024) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2024.3470211 · Cited by 22

Hardware/Software Co-Design With ADC-Less In-Memory Computing Hardware for Spiking Neural Networks

Apolinario, M. P. E., Kosta, A. K., Saxena, U., & Roy, K. (2023) · IEEE Transactions on Emerging Topics in Computing · doi:10.1109/tetc.2023.3316121 · Cited by 22

MAC-ECC: In-Situ Error Correction and Its Design Methodology for Reliable NVM-Based Compute-in-Memory Inference Engine

Li, W., Read, J., Jiang, H., & Yu, S. (2022) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2022.3223031 · Cited by 18

Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros

Sun, X., Cao, W., Crafton, B., Akarvardar, K., Mori, H., Fujiwara, H., Noguchi, H., Chih, Y.-D., Chang, M., Wang, Y., et al. (2023) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2023.3333290 · Cited by 18

Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators

Huang, S., Jiang, H., & Yu, S. (2022) · ACM Transactions on Design Automation of Electronic Systems · doi:10.1145/3569940 · Cited by 13

Achieving high precision in analog in-memory computing systems

Mannocci, P., Larelli, G., Bonomi, M., & Ielmini, D. (2026) · npj Unconventional Computing · doi:10.1038/s44335-025-00044-2 · Cited by 11

A High-Parallelism RRAM-Based Compute-In-Memory Macro With Intrinsic Impedance Boosting and In-ADC Computing

Xie, T., Yu, S., & Li, S. (2023) · IEEE Journal on Exploratory Solid-State Computational Devices and Circuits · doi:10.1109/jxcdc.2023.3255788 · Cited by 11

Light-CIM: A Lightweight ADC/DAC-Fewer RRAM CIM DNN Accelerator With Fully Analog Tiles and Nonideality-Aware Algorithm for Consumer Electronics

Zhao, C., Fang, J., Jiang, J., Xue, X., & Zeng, X. (2024) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2024.3435690 · Cited by 10

CMOS-compatible flash-gated thyristor–based neuromorphic module with small area and low energy consumption for in-memory computing

Ko, J., Im, J., Kim, J., Shin, W., Koo, R., Park, S., Woo, S. Y., & Lee, J. (2025) · Science Advances · doi:10.1126/sciadv.adt8227 · Cited by 8

A 28-nm 3.32-nJ/Frame Compute-in-Memory CNN Processor With Layer Fusion for Always-on Applications

Zhao, Y., He, P., Zhu, Y., Martins, R. P., Chan, C., & Zhang, M. (2025) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2025.3542590 · Cited by 6

A 0.0025mm2 8-bit 70MS/s SAR ADC with a Linearity-Improved Bootstrapped Switch for Computation in Memory

Xu, X., Shui, Y., & Wang, A. (2023) · International Conference on Integrated Circuits and Microsystems (ICICM) · doi:10.1109/icicm59499.2023.10365851 · Cited by 6

Enhancing AI Acceleration: A Calibration-Free, PVT-Robust Analog Compute-in-Memory Macro With Activation Functions

Wang, H., Liu, R., Dorrance, R., Dasalukunte, D., Gowda, N. M., & Carlton, B. R. (2024) · IEEE Solid-State Circuits Letters · doi:10.1109/lssc.2024.3510679 · Cited by 5

Vector-Matrix Multiplier Architecture for In-Memory Computing Applications With RRAM Arrays

Boro, B., Parmar, R., & Trivedi, G. (2025) · IEEE Transactions on Nanotechnology · doi:10.1109/tnano.2025.3560912 · Cited by 5

Devices, Materials, Process Technologies, and Microelectronic Ecosystem Beyond the Exit of the Device Miniaturization Tunnel

Wong, H. ‐. P., & Mitra, S. (2024) · IEEE Transactions on Materials for Electron Devices · doi:10.1109/tmat.2024.3484369 · Cited by 4

LIORAT: NN Layer I/O Range Training for Area/Energy-Efficient Low-Bit A/D Conversion System Design in Error-Tolerant Computation-in-Memory

Yamada, A., Misawa, N., Matsui, C., & Takeuchi, K. (2023) · doi:10.1109/iccad57390.2023.10323664 · Cited by 4

Impact of Gate/Drain Biases in FDSOI-Based Analog Synapse on Artificial Neural-Network Performance

Wang, W., Xu, S., Ye, J., Zhao, J., Qu, J., Loubriat, S., Besnard, G., Maleville, C., Weber, O., Arnaud, F., et al. (2025) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2025.3540764 · Cited by 4

Optimization Strategies for Digital Compute-in-Memory from Comparative Analysis with Systolic Array

Li, W., Lee, J., & Yu, S. (2023) · IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) · doi:10.1109/aicas57966.2023.10168651 · Cited by 4

A cold-electrode metal–oxide resistive random access memory

Cao, J., Chen, B., Wang, Z., Qu, J., Zhao, J., Shen, R., Yu, X., Yu, Z., & Liu, F. (2024) · Applied Physics Letters · doi:10.1063/5.0214593 · Cited by 4

A Spike Sorting SoC With Δ-Based Spike Detection and End-to-End Implementation of Autoencoder Feature Extraction Using Analog CIM

Lukito, V., Choi, E. J., Chang, I., Ha, S., & Je, M. (2025) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2025.3589523 · Cited by 3

A 1.1-nJ/Classification True Analog Current Computing on Multilayer Neural Network With Crystalline-IGZO/Si-CMOS Monolithic Stack Technology

Tsuda, K., Furutani, K., Yakubo, Y., Godo, H., Ando, Y., Kosuge, A., Nakura, T., & Yamazaki, S. (2024) · IEEE Journal of the Electron Devices Society · doi:10.1109/jeds.2024.3439712 · Cited by 3

Specific ADC of NVM-Based Computation-in-Memory for Deep Neural Networks

Shi, A., Zhang, Y., Han, L., Zhou, Z., Chen, Y., Yang, H., Liu, L., Shen, L., Liu, X., Kang, J., et al. (2024) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2024.3430290 · Cited by 3

Historical perspective and opportunity for computing in memory using floating-gate and resistive non-volatile computing including neuromorphic computing

Hasler, J., & Basu, A. (2024) · Neuromorphic Computing and Engineering · doi:10.1088/2634-4386/ad9b4a · Cited by 3

Low Quantization Error Readout Circuit with Fully Charge-Domain Calculation for Computation-in-Memory Deep Neural Network

Shi, A., Zhang, Y., Han, L., Zhou, Z., Chen, Y., Liu, L., Shen, L., Huang, P. C., Liu, X., & Kang, J. (2024) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas58744.2024.10558346 · Cited by 2

Inner Product Accelerating Scheme Based on RRAM Array for Attention-Mechanism Neural Network

Chen, Y., Han, L., Zhang, Y., Zhou, Z., Huang, P. C., Li, C., Liu, L., & Kang, J. (2024) · IEEE Electron Device Letters · doi:10.1109/led.2024.3352087 · Cited by 2

Optimizing and Exploring System Performance in Compact Processing-in-Memory-based Chips

Chen, P., & Yang, X. (2025) · IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) · doi:10.1109/aicas64808.2025.11173147 · Cited by 2

REM-CiM: Attentional RGB-Event Fusion Multi-Modal Analog CiM for Area/Energy-Efficient Edge Object Detection during Both Day and Night

ICHIKAWA, Y., Yamada, A., Misawa, N., Matsui, C., & TAKEUCHI, K. (2024) · IEICE Transactions on Electronics · doi:10.1587/transele.2023ctp0001 · Cited by 2

Stable On-Chip MLC RRAM With a Bitline Regulation-Free Analog MAC Scheme for High-Efficiency In-Memory Computing

Kong, Z., Lan, J., Li, H., Yang, Z., Dong, W.-K., He, J., Lyu, H., Wang, X., Zhu, Y., Jain, S., et al. (2026) · IEEE Electron Device Letters · doi:10.1109/led.2026.3680336 · Cited by 1

MeMCISA: Memristor-Enabled Memory-Centric Instruction-Set Architecture for Database Workloads

Zhu, Y., Cai, L., Yu, L., Fan, A., Yan, L., Jing, Z., Yan, B., Tiw, P. J., Li, Y., Tao, Y., et al. (2024) · IEEE/ACM International Symposium on Microarchitecture (MICRO) · doi:10.1109/micro61859.2024.00122 · Cited by 1

Neuromorphic Denoising with Fully Analog Memristive In‐Memory Computing

Shi, D., Zhang, T., Li, Y., Tao, Y., Yan, B. Y., & Yang, Y. (2026) · Advanced Intelligent Systems · doi:10.1002/aisy.70419 · Cited by 1

Straightforward data transfer in a blockwise dataflow for an analog RRAM-based CIM system

Liu, Y., Gao, B., Yao, P., Liu, Q., Zhang, Q., Wu, D. M., Tang, J., Qian, H., & Wu, H. (2023) · Frontiers in Electronics · doi:10.3389/felec.2023.1129675 · Cited by 1

Enabling Ultra-Low Power Ultrasound Imaging with Compute-in-Memory Sparse Reconstruction Accelerator

Li, W., Zhang, X., Lee, J., Degertekin, F. L., Li, S., & Yu, S. (2023) · IEEE Biomedical Circuits and Systems Conference (BioCAS) · doi:10.1109/biocas58349.2023.10389000 · Cited by 1

RGB-Event Multi-Modal NV-CiM to Detect Object by Mapping-Oriented Enhanced-Feature Pyramid Network with Mapping-Aware Group Convolution

ICHIKAWA, Y., Misawa, N., MATSUI, C., & Takeuchi, K. (2024) · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences · doi:10.1587/transfun.2024vlp0013 · Cited by 1

Programmable Binary Weighted Time-Domain Vector Matrix Multiplier for In-Memory Computing

Boro, B., Dongre, A., Parmar, R., & Trivedi, G. (2023) · IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) · doi:10.1109/apccas60141.2023.00066

Reprogrammable Time-Domain RRAM Based Vector Matrix Multiplier for In-Memory Computing

Boro, B., Parmar, R., Dongre, A., & Trivedi, G. (2024) · International Symposium on Quality Electronic Design (ISQED) · doi:10.1109/isqed60706.2024.10528699

Analog Computing with High Precision and Reliability (Invited)

Song, W., & Yang, J. J. (2025) · IEEE International Reliability Physics Symposium proceedings · doi:10.1109/irps48204.2025.10983907

High Energy-efficiency and Low latency In-Memory Computing using Analog Accumulator and In-Memory ADC with shared References

Yang, J., Dong, S., Fu, Z., Shang, H., & Basu, A. (2025) · ACM/IEEE Design Automation Conference (DAC) · doi:10.1109/dac63849.2025.11133014

Analysis and Design of Memory Testing Algorithm for Computing-in-Memory Using MBIST

Lin, Z., Li, S., Zhang, Q., Feng, Q., Yue, C., Chen, J., Wang, Y., Liu, Y., Liu, Y., Hao, L., et al. (2025) · ACM Journal on Emerging Technologies in Computing Systems · doi:10.1145/3766540

A Fully Analog Computing-in-Memory Macro With INT8-MAC Operations for Edge-AI Device

Huang, W.-C., Chien, H.-T., Chang, S.-J., Hu, J.-H., & Kuo, C.-H. (2026) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2026.3657011

Activation‐Integrated and Memory‐Assisted Dynamic‐Latch Quantizer for Variation‐Tolerant and Low‐Energy Neuromorphic Computing

Ko, J., Im, J., Koo, R., Park, S., & Lee, J. (2026) · Advanced Intelligent Systems · doi:10.1002/aisy.202501499

An SOT-MRAM-Based Δ-Bias-Σ Computing Paradigm for High Energy Efficiency Computer Vision Applications

Wang, S., Fang, Z.-Q., Du, H., Zhang, R., Zhu, H., Liu, B., & Cai, H. (2026) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2026.3674531

Non-Destructive Read-Out FeRAM Cell and Architecture for Compute-in-memory Applications

Zhou, Y., Zhong, J., Tan, W., Xu, Y., Chen, J. M., Zuo, J., Peng, C., & Wu, X. (2026) · International Symposium on Intelligent Robotics and Systems (ISoIRS) · doi:10.1109/isoirs70157.2026.11545251

NOVA-PIM: Noise-Aware Hyperdimensional Processing in Memory with Optimized Vector Allocation and Minimal ADCs

Fan, K., Song, C. E., Wang, X., Rosing, T., & Kang, M. (2026) · ACM Great Lakes Symposium on VLSI (GLSVLSI) · doi:10.1145/3787109.3815224

A Data-Driven Framework for Modeling Non-Idealities in Analog In-Memory Computing Hardware

Vasilopoulos, A., Kersting, B., Büchel, J., Sebastian, A., & Gallo, M. L. (2026) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2026.3705427

A Differentiable Simulator for Optimizing Time-Domain Analog CNN Accelerators

Horton, M., Park, C., Molom-Ochir, T., McGarry, W., Gu, J., & Chen, Y. (2026) · International Symposium on Low Power Electronics and Design (ISLPED) · doi:10.1145/3816440.3828510

S 2 -CIM: A 53.9 TOPS/W SRAM-based Sign-bit-Aware Multibit Compute-In-Memory Architecture for Edge-AI Inference

Singla, A., Chithambara Moorthii, J., Shaik, S. A., Dey, S., Mukherjee, A., Pal, A., & Suri, M. (2026) · IEEE Interregional NEWCAS Conference (NEWCAS) · doi:10.1109/newcas64543.2026.11674054

ADC-Free Current-Domain Compute-In-Memory Processors for Intelligent Image Sensing

Gupte, K. K., Chen, D. J., & Wang, C. (2026) · IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) · doi:10.1109/mwscas67364.2026.11680770

Memristive In-Memory Computing for AI: Neural Network Acceleration, Adaptive Learning, and System Integration

Dong, C., Xie, X., Chen, J., Tan, G., Huang, Y., & Cao, S. (2026) · Electronics · doi:10.3390/electronics15194512

ECC-Assisted Fault Tolerance in Memristive Crossbar-based CIM Architectures: An Overview

Hemaram, S., Hamdioui, S., & Gebregiorgis, A. (2026) · IFIP/IEEE International Conference on Very Large Scale Integration · doi:10.1109/vlsi-soc70418.2026.11740617

A High-Parallelism RRAM-Based Compute-In-Memory Macro With Intrinsic Impedance Boosting and In-ADC Computing

Xie, T., Yu, S., & Li, S. (2023) · IEEE Journal on Exploratory Solid-State Computational Devices and Circuits · doi:10.1109/jxcdc.2023.3255788 · Cited by 11

A Robust Computing-in-Memory Macro With 2T1R1C Cells and Reused Capacitors for Successive-Approximation ADC

Xiao, R., Jiang, M. Z., Li, X., Shen, H., & Huang, K. (2025) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2025.3539826 · Cited by 8

A 28 nm 576K RRAM-based computing-in-memory macro featuring hybrid programming with area efficiency of 2.82 TOPS/mm2

Liu, S., Wei, S.-T., Yao, P., Wu, D. M., Lu, J., Pan, S., Tang, J., Gao, B., Qian, H., & Wu, H. (2025) · Journal of Semiconductors · doi:10.1088/1674-4926/24100017 · Cited by 5

A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications

Xiao, K., Cui, X., Qiao, X., Wang, X., & Wang, Y. (2022) · Microelectronics Journal · doi:10.1016/j.mejo.2022.105506 · Cited by 12

A 44.3 TOPS/W SRAM Compute-in-Memory With Near-CIM Analog Memory and Activation for DAC/ADC-Less Operations

Chen, P., Wu, M., Zhao, W., Ma, Y., Jia, T., & Ye, L. (2024) · IEEE Solid-State Circuits Letters · doi:10.1109/lssc.2024.3418099 · Cited by 14